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Update design files: modify timestamps, enhance signal connections, and improve comments for clarity; remove archived project files

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Davide Cavagnola
2025-04-25 22:18:03 +02:00
parent 14a6be00d6
commit 31f66ef8d1
7 changed files with 27 additions and 23 deletions
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2
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 10:55:47 2025
--Date : Fri Apr 25 22:08:38 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper

14
LAB2/design/lab_2/lab_2.bd
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@@ -1169,6 +1169,13 @@
}
},
"interface_nets": {
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
},
"img_conv_0_m_axis": {
"interface_ports": [
"img_conv_0/m_axis",
@@ -1200,13 +1207,6 @@
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
}
},
"nets": {

16
LAB2/design/lab_2/lab_2.bda
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@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">lab_2</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
<node id="n2">
<data key="VH">2</data>
<data key="VM">lab_2</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n1" target="n2">
</edge>
<edge id="e1" source="n0" target="n1">
<edge id="e1" source="n2" target="n0">
</edge>
</graph>
</graphml>