Update design files: modify timestamps, enhance signal connections, and improve comments for clarity; remove archived project files

This commit is contained in:
2025-04-25 22:18:03 +02:00
parent 14a6be00d6
commit 31f66ef8d1
7 changed files with 27 additions and 23 deletions

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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 10:55:47 2025
--Date : Fri Apr 25 22:08:38 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper