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Update design files: modify timestamps, enhance signal connections, and improve comments for clarity; remove archived project files

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This commit is contained in:
Davide Cavagnola
2025-04-25 22:18:03 +02:00
parent 14a6be00d6
commit 31f66ef8d1
7 changed files with 27 additions and 23 deletions
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6
LAB2/src/divider_by_3.vhd
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@@ -25,13 +25,13 @@ ARCHITECTURE Behavioral OF divider_by_3 IS
SIGNAL mult_result : UNSIGNED(MULT_WIDTH - 1 DOWNTO 0);
SIGNAL sum_with_offset : UNSIGNED(MULT_WIDTH - 1 DOWNTO 0);
BEGIN
-- Moltiplicazione senza perdita di bit
-- Multiplication without loss of bits
mult_result <= dividend * TO_UNSIGNED(DIVISION_MULTIPLIER, N - 1);
-- Somma con offset senza perdita di bit
-- Addition with offset, no loss of bits
sum_with_offset <= mult_result + TO_UNSIGNED(OFFSET, MULT_WIDTH);
-- Estrazione risultato arrotondato
-- Extract rounded result
result <= sum_with_offset(MULT_WIDTH - 2 DOWNTO MULT_WIDTH - BIT_DEPTH -1);
END Behavioral;

12
LAB2/src/rgb2gray.vhd
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@@ -50,12 +50,13 @@ ARCHITECTURE Behavioral OF rgb2gray IS
BEGIN
-- Connect internal signals to output ports
s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int;
m_axis_tdata <= m_axis_tdata_int;
m_axis_tlast <= m_axis_tlast_int;
-- Divider instance
-- Divider instance: divides the sum of RGB by 3 to obtain grayscale value
DIVIDER : divider_by_3
GENERIC MAP(
BIT_DEPTH => 7
@@ -69,6 +70,7 @@ BEGIN
BEGIN
IF rising_edge(clk) THEN
IF resetn = '0' THEN
-- Asynchronous reset: initialize all signals and state
state <= IDLE;
sum <= (OTHERS => '0');
rgb_sum <= (OTHERS => '0');
@@ -79,11 +81,12 @@ BEGIN
s_axis_tready_int <= '1';
last_seen <= '0';
ELSE
-- Default assignments
-- Default assignments for each clock cycle
m_axis_tlast_int <= '0';
CASE state IS
WHEN IDLE =>
-- Wait for the first valid input sample
m_axis_tdata_int <= (OTHERS => '0');
sum <= (OTHERS => '0');
count <= 0;
@@ -99,6 +102,7 @@ BEGIN
END IF;
WHEN ACCUMULATE =>
-- Accumulate the next two color components (expecting 3 total: R, G, B)
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= sum + unsigned(s_axis_tdata);
IF count = 2 THEN
@@ -117,7 +121,7 @@ BEGIN
END IF;
WHEN WAIT_DIV =>
-- Ora gray <EFBFBD> valido
-- Now gray is valid (output from divider)
m_axis_tdata_int <= '0' & STD_LOGIC_VECTOR(gray);
m_axis_tvalid_int <= '1';
s_axis_tready_int <= '0';
@@ -128,7 +132,7 @@ BEGIN
state <= SEND;
WHEN SEND =>
-- Mantieni il dato finch<63> non viene accettato
-- Hold the data until it is accepted by the downstream module
IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';