Add pak_depak design files and update project references
- Created new design file `pak_depak.bd` with components including `proc_sys_reset`, `clk_wiz`, `AXI4Stream_UART`, `depacketizer`, and `packetizer`. - Added associated architecture file `pak_depak.bda` for design representation. - Introduced UI configuration file `bd_c9b29a54.ui` for graphical representation of the design. - Updated project file `lab2.xpr` to replace references to old source files with new ones. - Added new project file `pak_depak.xpr` for the pak_depak design with necessary configurations and file sets.
This commit is contained in:
398
LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd
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398
LAB2/src/pak_depak/ipshared/453d/hdl/AXI4Stream_UART_v1_0.vhd
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@@ -0,0 +1,398 @@
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---- * ) ----
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----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
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---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
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----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
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----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
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---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
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---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
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---- |___/ |___/ ----
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-------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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---- _____ _ ___ __ _ _ _ __ _ ----
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---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
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---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
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---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
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---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
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----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------------------------------------------------
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-------------------------------------DESCRIPTION------------------------------------------
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------------------------------------------------------------------------------------------
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-- Bridge FT245Async to AXI4-Stream. --
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------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library xpm;
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use xpm.vcomponents.all;
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entity AXI4Stream_UART_v1_0 is
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generic (
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------------------UART PARAMETER-------------------
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UART_BAUD_RATE : positive := 115_200;
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UART_CLOCK_FREQUENCY : positive := 100_000_000; --The associated clock frequency
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----------------------------------------------------
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-- Parameters of Axi Master Bus Interface M00_AXIS_RX
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C_M00_AXIS_RX_TDATA_WIDTH : integer := 8;
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-- Parameters of Axi Slave Bus Interface S00_AXIS_TX
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C_S00_AXIS_TX_TDATA_WIDTH : integer := 8
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);
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port (
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---------Global---------
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clk_uart : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX : OUT STD_LOGIC;
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UART_RX : IN STD_LOGIC;
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---------------------------------------------------
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---Ports of Axi Master Bus Interface M00_AXIS_RX---
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m00_axis_rx_aclk : IN STD_LOGIC;
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m00_axis_rx_aresetn : IN STD_LOGIC;
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m00_axis_rx_tvalid : OUT STD_LOGIC;
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m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0);
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m00_axis_rx_tready : IN STD_LOGIC;
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--------------------------------------------------
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---Ports of Axi Slave Bus Interface S00_AXIS_TX---
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s00_axis_tx_aclk : IN STD_LOGIC;
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s00_axis_tx_aresetn : IN STD_LOGIC;
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s00_axis_tx_tready : OUT STD_LOGIC;
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s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0);
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s00_axis_tx_tvalid : IN STD_LOGIC
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--------------------------------------------------
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);
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end AXI4Stream_UART_v1_0;
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architecture arch_imp of AXI4Stream_UART_v1_0 is
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--------------------------------COMPONENTS DECLARATION-----------------------------------
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component UART_Manager is
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generic(
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UART_BAUD_RATE : positive;
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UART_CLOCK_FREQUENCY : positive --The associated clock frequency
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);
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Port (
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---------Global---------
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clk_uart : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX : OUT STD_LOGIC;
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UART_RX : IN STD_LOGIC;
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---------------------------------------------------
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------------FIFO_DATA_RX (8bit)-------------
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FIFO_DATA_RX_rst : OUT STD_LOGIC;
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FIFO_DATA_RX_clk : OUT STD_LOGIC;
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FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
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FIFO_DATA_RX_full : IN STD_LOGIC;
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FIFO_DATA_RX_almost_full : IN STD_LOGIC;
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--------------------------------------------
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------------FIFO_DATA_TX (8bit)-------------
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--FIFO_DATA_RX_rst : OUT STD_LOGIC;
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FIFO_DATA_TX_clk : OUT STD_LOGIC;
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FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
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FIFO_DATA_TX_empty : IN STD_LOGIC;
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FIFO_DATA_TX_almost_empty : IN STD_LOGIC
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--------------------------------------------
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);
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end component UART_Manager;
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component AXI4Stream_UART_v1_0_M00_AXIS_RX is
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generic (
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-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
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C_M_AXIS_TDATA_WIDTH : integer := 8
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);
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port (
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--------------FIFO_DATA (8bit)--------------
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--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
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FIFO_DATA_clk : OUT STD_LOGIC;
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FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
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FIFO_DATA_rd_en : OUT STD_LOGIC;
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FIFO_DATA_empty : IN STD_LOGIC;
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FIFO_DATA_almost_empty : IN STD_LOGIC;
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream Clock
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M_AXIS_ACLK : IN STD_LOGIC;
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-- AXI4Stream Reset
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M_AXIS_ARESETN : IN STD_LOGIC;
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-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
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M_AXIS_TVALID : OUT STD_LOGIC;
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-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
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M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
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-- TREADY indicates that the slave can accept a transfer in the current cycle.
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M_AXIS_TREADY : IN STD_LOGIC
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--------------------------------------------
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);
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end component AXI4Stream_UART_v1_0_M00_AXIS_RX;
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component AXI4Stream_UART_v1_0_S00_AXIS_TX is
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generic (
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-- AXI4Stream sink: Data Width
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C_S_AXIS_TDATA_WIDTH : integer := 8
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);
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port (
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--------------FIFO_DATA-------------
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FIFO_DATA_rst : OUT STD_LOGIC;
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FIFO_DATA_clk : OUT STD_LOGIC;
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FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
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FIFO_DATA_wr_en : OUT STD_LOGIC;
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FIFO_DATA_full : IN STD_LOGIC;
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FIFO_DATA_almost_full : IN STD_LOGIC;
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream sink: Clock
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S_AXIS_ACLK : IN STD_LOGIC;
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-- AXI4Stream sink: Reset
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S_AXIS_ARESETN : IN STD_LOGIC;
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-- Ready to accept data in
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S_AXIS_TREADY : OUT STD_LOGIC;
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-- Data in
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S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
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-- Data is in valid
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S_AXIS_TVALID : IN STD_LOGIC
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--------------------------------------------
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);
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end component AXI4Stream_UART_v1_0_S00_AXIS_TX;
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-----------------------------------------------------------------------------------------
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---------------------------------------SIGNALS-------------------------------------------
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-----------------FIFO_DATA_RX-----------------
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signal FIFO_DATA_RX_rst : STD_LOGIC;
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signal FIFO_DATA_RX_wr_clk : STD_LOGIC;
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signal FIFO_DATA_RX_rd_clk : STD_LOGIC;
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signal FIFO_DATA_RX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_RX_wr_en : STD_LOGIC;
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signal FIFO_DATA_RX_rd_en : STD_LOGIC;
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signal FIFO_DATA_RX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_RX_full : STD_LOGIC;
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signal FIFO_DATA_RX_almost_full : STD_LOGIC;
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signal FIFO_DATA_RX_empty : STD_LOGIC;
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signal FIFO_DATA_RX_almost_empty : STD_LOGIC;
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----------------------------------------------
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-----------------FIFO_DATA_TX-----------------
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signal FIFO_DATA_TX_rst : STD_LOGIC;
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signal FIFO_DATA_TX_wr_clk : STD_LOGIC;
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signal FIFO_DATA_TX_rd_clk : STD_LOGIC;
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signal FIFO_DATA_TX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_TX_wr_en : STD_LOGIC;
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signal FIFO_DATA_TX_rd_en : STD_LOGIC;
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signal FIFO_DATA_TX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
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signal FIFO_DATA_TX_full : STD_LOGIC;
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signal FIFO_DATA_TX_almost_full : STD_LOGIC;
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signal FIFO_DATA_TX_empty : STD_LOGIC;
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signal FIFO_DATA_TX_almost_empty : STD_LOGIC;
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----------------------------------------------
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-----------------------------------------------------------------------------------------
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begin
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-----------------------MODULE INSTANTIATION-------------------------
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AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX
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generic map(
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-- AXI4Stream sink: Data Width
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C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TX_TDATA_WIDTH
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)
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port map(
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--------------FIFO_DATA-------------
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FIFO_DATA_rst => FIFO_DATA_TX_rst,
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FIFO_DATA_clk => FIFO_DATA_TX_wr_clk,
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FIFO_DATA_din => FIFO_DATA_TX_din,
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FIFO_DATA_wr_en => FIFO_DATA_TX_wr_en,
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FIFO_DATA_full => FIFO_DATA_TX_full,
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FIFO_DATA_almost_full => FIFO_DATA_TX_almost_full,
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--------------------------------------------
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----------------AXI4-Stream-----------------
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-- AXI4Stream sink: Clock
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S_AXIS_ACLK => s00_axis_tx_aclk,
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-- AXI4Stream sink: Reset
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S_AXIS_ARESETN => s00_axis_tx_aresetn,
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-- Ready to accept data in
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S_AXIS_TREADY => s00_axis_tx_tready,
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-- Data in
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S_AXIS_TDATA => s00_axis_tx_tdata,
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-- Data is in valid
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S_AXIS_TVALID => s00_axis_tx_tvalid
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--------------------------------------------
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);
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-- xpm_fifo_async: Asynchronous FIFO
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-- Xilinx Parameterized Macro, Version 2017.3
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FIFO_DATA_TX : xpm_fifo_async
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generic map (
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FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
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FIFO_WRITE_DEPTH => 2048, --positive integer;
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RELATED_CLOCKS => 0, --positive integer; 0 or 1;
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WRITE_DATA_WIDTH => 8, --positive integer;
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WR_DATA_COUNT_WIDTH => 1, --positive integer;
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READ_MODE => "fwft", --string; "std" or "fwft";
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FIFO_READ_LATENCY => 0, --positive integer;
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--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
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READ_DATA_WIDTH => 8, --positive integer;
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RD_DATA_COUNT_WIDTH => 1, --positive integer;
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CDC_SYNC_STAGES => 2, --positive integer;
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ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
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--PROG_FULL_THRESH => 10, --positive integer
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--PROG_EMPTY_THRESH => 10, --positive integer
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--DOUT_RESET_VALUE => "0", --string
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WAKEUP_TIME => 0, --positive integer; 0 or 2;
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USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
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)
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port map (
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wr_clk => FIFO_DATA_TX_wr_clk,
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wr_en => FIFO_DATA_TX_wr_en,
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din => FIFO_DATA_TX_din,
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full => FIFO_DATA_TX_full,
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overflow => open,
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wr_rst_busy => open,
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sleep => '0',
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rst => FIFO_DATA_TX_rst,
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rd_clk => FIFO_DATA_TX_rd_clk,
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rd_en => FIFO_DATA_TX_rd_en,
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dout => FIFO_DATA_TX_dout,
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empty => FIFO_DATA_TX_empty,
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underflow => open,
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rd_rst_busy => open,
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injectsbiterr => '0',
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injectdbiterr => '0',
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almost_full => FIFO_DATA_TX_almost_full,
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almost_empty => FIFO_DATA_TX_almost_empty
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);
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UART_Manager_inst : UART_Manager
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Generic map(
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UART_BAUD_RATE => UART_BAUD_RATE,
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UART_CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
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)
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Port map(
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---------Global---------
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clk_uart => clk_uart,
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reset => rst,
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------------------------
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---------Connessioni comunicazione UART-----------
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UART_TX => UART_TX,
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UART_RX => UART_RX,
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||||
---------------------------------------------------
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|
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------------FIFO_DATA_RX (8bit)-------------
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FIFO_DATA_RX_rst => FIFO_DATA_RX_rst,
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FIFO_DATA_RX_clk => FIFO_DATA_RX_wr_clk,
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FIFO_DATA_RX_din => FIFO_DATA_RX_din,
|
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FIFO_DATA_RX_wr_en => FIFO_DATA_RX_wr_en,
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FIFO_DATA_RX_full => FIFO_DATA_RX_full,
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FIFO_DATA_RX_almost_full => FIFO_DATA_RX_almost_full,
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--------------------------------------------
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------------FIFO_DATA_TX (8bit)-------------
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FIFO_DATA_TX_clk => FIFO_DATA_TX_rd_clk,
|
||||
FIFO_DATA_TX_dout => FIFO_DATA_TX_dout,
|
||||
FIFO_DATA_TX_rd_en => FIFO_DATA_TX_rd_en,
|
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FIFO_DATA_TX_empty => FIFO_DATA_TX_empty,
|
||||
FIFO_DATA_TX_almost_empty => FIFO_DATA_TX_almost_empty
|
||||
--------------------------------------------
|
||||
);
|
||||
|
||||
-- xpm_fifo_async: Asynchronous FIFO
|
||||
-- Xilinx Parameterized Macro, Version 2017.3
|
||||
FIFO_DATA_RX : xpm_fifo_async
|
||||
generic map (
|
||||
FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
|
||||
FIFO_WRITE_DEPTH => 2048, --positive integer;
|
||||
RELATED_CLOCKS => 0, --positive integer; 0 or 1;
|
||||
WRITE_DATA_WIDTH => 8, --positive integer;
|
||||
WR_DATA_COUNT_WIDTH => 1, --positive integer;
|
||||
READ_MODE => "fwft", --string; "std" or "fwft";
|
||||
FIFO_READ_LATENCY => 0, --positive integer;
|
||||
--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
|
||||
READ_DATA_WIDTH => 8, --positive integer;
|
||||
RD_DATA_COUNT_WIDTH => 1, --positive integer;
|
||||
CDC_SYNC_STAGES => 2, --positive integer;
|
||||
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
|
||||
--PROG_FULL_THRESH => 10, --positive integer
|
||||
--PROG_EMPTY_THRESH => 10, --positive integer
|
||||
--DOUT_RESET_VALUE => "0", --string
|
||||
WAKEUP_TIME => 0, --positive integer; 0 or 2;
|
||||
USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
|
||||
)
|
||||
port map (
|
||||
wr_clk => FIFO_DATA_RX_wr_clk,
|
||||
wr_en => FIFO_DATA_RX_wr_en,
|
||||
din => FIFO_DATA_RX_din,
|
||||
full => FIFO_DATA_RX_full,
|
||||
overflow => open,
|
||||
wr_rst_busy => open,
|
||||
sleep => '0',
|
||||
rst => FIFO_DATA_RX_rst,
|
||||
rd_clk => FIFO_DATA_RX_rd_clk,
|
||||
rd_en => FIFO_DATA_RX_rd_en,
|
||||
dout => FIFO_DATA_RX_dout,
|
||||
empty => FIFO_DATA_RX_empty,
|
||||
underflow => open,
|
||||
rd_rst_busy => open,
|
||||
injectsbiterr => '0',
|
||||
injectdbiterr => '0',
|
||||
almost_full => FIFO_DATA_RX_almost_full,
|
||||
almost_empty => FIFO_DATA_RX_almost_empty
|
||||
);
|
||||
|
||||
AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX
|
||||
generic map(
|
||||
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
|
||||
C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_RX_TDATA_WIDTH
|
||||
|
||||
)
|
||||
port map(
|
||||
--------------FIFO_DATA (8bit)--------------
|
||||
FIFO_DATA_clk => FIFO_DATA_RX_rd_clk,
|
||||
FIFO_DATA_dout => FIFO_DATA_RX_dout,
|
||||
FIFO_DATA_rd_en => FIFO_DATA_RX_rd_en,
|
||||
FIFO_DATA_empty => FIFO_DATA_RX_empty,
|
||||
FIFO_DATA_almost_empty => FIFO_DATA_RX_almost_empty,
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream Clock
|
||||
M_AXIS_ACLK => m00_axis_rx_aclk,
|
||||
-- AXI4Stream Reset
|
||||
M_AXIS_ARESETN => m00_axis_rx_aresetn,
|
||||
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
|
||||
M_AXIS_TVALID => m00_axis_rx_tvalid,
|
||||
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
|
||||
M_AXIS_TDATA => m00_axis_rx_tdata,
|
||||
-- TREADY indicates that the slave can accept a transfer in the current cycle.
|
||||
M_AXIS_TREADY => m00_axis_rx_tready
|
||||
--------------------------------------------
|
||||
);
|
||||
|
||||
--------------------------------------------------------------------
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,91 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Bridge da FIFO 8bit to AXI4 Stream. --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity AXI4Stream_UART_v1_0_M00_AXIS_RX is
|
||||
generic (
|
||||
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
|
||||
C_M_AXIS_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
--------------FIFO_DATA (8bit)--------------
|
||||
--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
|
||||
FIFO_DATA_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_rd_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_empty : IN STD_LOGIC;
|
||||
FIFO_DATA_almost_empty : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream Clock
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
-- AXI4Stream Reset
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
-- TREADY indicates that the slave can accept a transfer in the current cycle.
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end AXI4Stream_UART_v1_0_M00_AXIS_RX;
|
||||
|
||||
architecture implementation of AXI4Stream_UART_v1_0_M00_AXIS_RX is
|
||||
|
||||
----------------------------SIGNALS-----------------------------
|
||||
signal M_AXIS_TVALID_int : STD_LOGIC;
|
||||
----------------------------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
---------DIRECT ASSIGNMENT----------
|
||||
FIFO_DATA_clk <= M_AXIS_ACLK;
|
||||
--FIFO_DATA_rst <= not M_AXIS_ARESETN;
|
||||
|
||||
M_AXIS_TDATA <= FIFO_DATA_dout;
|
||||
|
||||
FIFO_DATA_rd_en <= M_AXIS_TREADY and M_AXIS_TVALID_int;
|
||||
|
||||
M_AXIS_TVALID_int <= not FIFO_DATA_empty and M_AXIS_ARESETN;
|
||||
M_AXIS_TVALID <= M_AXIS_TVALID_int;
|
||||
|
||||
------------------------------------
|
||||
|
||||
end implementation;
|
||||
@@ -0,0 +1,90 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Bridge da FIFO 8bit to AXI4 Stream. --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity AXI4Stream_UART_v1_0_S00_AXIS_TX is
|
||||
generic (
|
||||
-- AXI4Stream sink: Data Width
|
||||
C_S_AXIS_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
|
||||
--------------FIFO_DATA (32bit)-------------
|
||||
FIFO_DATA_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
FIFO_DATA_wr_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_full : IN STD_LOGIC;
|
||||
FIFO_DATA_almost_full : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream sink: Clock
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
-- AXI4Stream sink: Reset
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
-- Ready to accept data in
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
-- Data in
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
-- Data is in valid
|
||||
S_AXIS_TVALID : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end AXI4Stream_UART_v1_0_S00_AXIS_TX;
|
||||
|
||||
architecture arch_imp of AXI4Stream_UART_v1_0_S00_AXIS_TX is
|
||||
|
||||
-----------------------------SIGNALS----------------------------
|
||||
signal S_AXIS_TREADY_int : STD_LOGIC;
|
||||
----------------------------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
---------DIRECT ASSIGNMENT----------
|
||||
FIFO_DATA_clk <= S_AXIS_ACLK;
|
||||
FIFO_DATA_rst <= not S_AXIS_ARESETN;
|
||||
|
||||
FIFO_DATA_din <= S_AXIS_TDATA;
|
||||
|
||||
FIFO_DATA_wr_en <= S_AXIS_TREADY_int and S_AXIS_TVALID;
|
||||
|
||||
S_AXIS_TREADY_int <= not FIFO_DATA_almost_full and S_AXIS_ARESETN;
|
||||
S_AXIS_TREADY <= S_AXIS_TREADY_int;
|
||||
------------------------------------
|
||||
|
||||
end arch_imp;
|
||||
343
LAB2/src/pak_depak/ipshared/453d/hdl/UART_Engine.vhd
Normal file
343
LAB2/src/pak_depak/ipshared/453d/hdl/UART_Engine.vhd
Normal file
@@ -0,0 +1,343 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:02:15 01/23/2016
|
||||
-- Design Name:
|
||||
-- Module Name: uart - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
-- UART
|
||||
-- Implements a universal asynchronous receiver transmitter
|
||||
-------------------------------------------------------------------------------
|
||||
-- clock
|
||||
-- Input clock, must match frequency value given on clock_frequency
|
||||
-- generic input.
|
||||
-- reset
|
||||
-- Synchronous reset.
|
||||
-- data_stream_in
|
||||
-- Input data bus for bytes to transmit.
|
||||
-- data_stream_in_stb
|
||||
-- Input strobe to qualify the input data bus.
|
||||
-- data_stream_in_ack
|
||||
-- Output acknowledge to indicate the UART has begun sending the byte
|
||||
-- provided on the data_stream_in port.
|
||||
-- data_stream_in_done
|
||||
-- Output pulse che arriva quando fine tx
|
||||
-- data_stream_out
|
||||
-- Data output port for received bytes.
|
||||
-- data_stream_out_stb
|
||||
-- Output strobe to qualify the received byte. Will be valid for one clock
|
||||
-- cycle only.
|
||||
-- tx
|
||||
-- Serial transmit.
|
||||
-- rx
|
||||
-- Serial receive
|
||||
-------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity UART_Engine is
|
||||
generic (
|
||||
BAUD_RATE : integer range 110 to 2000000;
|
||||
CLOCK_FREQUENCY : positive
|
||||
);
|
||||
port (
|
||||
clock : in std_logic;
|
||||
reset : in std_logic;
|
||||
data_stream_in : in std_logic_vector(7 downto 0);
|
||||
data_stream_in_stb : in std_logic;
|
||||
data_stream_in_ack : out std_logic;
|
||||
data_stream_in_done : out std_logic;
|
||||
data_stream_out : out std_logic_vector(7 downto 0);
|
||||
data_stream_out_stb : out std_logic;
|
||||
tx : out std_logic;
|
||||
rx : in std_logic
|
||||
);
|
||||
end UART_Engine;
|
||||
|
||||
architecture rtl of UART_Engine is
|
||||
---------------------------------------------------------------------------
|
||||
-- Baud generation constants
|
||||
---------------------------------------------------------------------------
|
||||
constant c_tx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE)));
|
||||
constant c_rx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16)));
|
||||
---------------------------------------------------------------------------
|
||||
-- Baud generation signals
|
||||
---------------------------------------------------------------------------
|
||||
signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0;
|
||||
signal tx_baud_tick : std_logic := '0';
|
||||
signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0;
|
||||
signal rx_baud_tick : std_logic := '0';
|
||||
---------------------------------------------------------------------------
|
||||
-- Transmitter signals
|
||||
---------------------------------------------------------------------------
|
||||
type uart_tx_states is (
|
||||
tx_send_start_bit,
|
||||
tx_send_data,
|
||||
tx_send_stop_bit
|
||||
);
|
||||
signal uart_tx_state : uart_tx_states := tx_send_start_bit;
|
||||
signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal uart_tx_data : std_logic := '1';
|
||||
signal uart_tx_count : unsigned(2 downto 0) := (others => '0');
|
||||
signal uart_rx_data_in_ack : std_logic := '0';
|
||||
signal uart_rx_data_in_done : std_logic := '0';
|
||||
---------------------------------------------------------------------------
|
||||
-- Receiver signals
|
||||
---------------------------------------------------------------------------
|
||||
type uart_rx_states is (
|
||||
rx_get_start_bit,
|
||||
rx_get_data,
|
||||
rx_get_stop_bit
|
||||
);
|
||||
signal uart_rx_state : uart_rx_states := rx_get_start_bit;
|
||||
signal uart_rx_bit : std_logic := '1';
|
||||
signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1');
|
||||
signal uart_rx_filter : unsigned(1 downto 0) := (others => '1');
|
||||
signal uart_rx_count : unsigned(2 downto 0) := (others => '0');
|
||||
signal uart_rx_data_out_stb : std_logic := '0';
|
||||
signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
|
||||
signal uart_rx_bit_tick : std_logic := '0';
|
||||
begin
|
||||
-- Connect IO
|
||||
data_stream_in_ack <= uart_rx_data_in_ack;
|
||||
data_stream_in_done <= uart_rx_data_in_done;
|
||||
data_stream_out <= uart_rx_data_vec;
|
||||
data_stream_out_stb <= uart_rx_data_out_stb;
|
||||
tx <= uart_tx_data;
|
||||
---------------------------------------------------------------------------
|
||||
-- OVERSAMPLE_CLOCK_DIVIDER
|
||||
-- generate an oversampled tick (baud * 16)
|
||||
---------------------------------------------------------------------------
|
||||
oversample_clock_divider : process (clock)
|
||||
begin
|
||||
if rising_edge (clock) then
|
||||
if reset = '1' then
|
||||
rx_baud_counter <= 0;
|
||||
rx_baud_tick <= '0';
|
||||
else
|
||||
if rx_baud_counter = c_rx_div - 1 then
|
||||
rx_baud_counter <= 0;
|
||||
rx_baud_tick <= '1';
|
||||
else
|
||||
rx_baud_counter <= rx_baud_counter + 1;
|
||||
rx_baud_tick <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process oversample_clock_divider;
|
||||
---------------------------------------------------------------------------
|
||||
-- RXD_SYNCHRONISE
|
||||
-- Synchronise rxd to the oversampled baud
|
||||
---------------------------------------------------------------------------
|
||||
rxd_synchronise : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_rx_data_sr <= (others => '1');
|
||||
else
|
||||
if rx_baud_tick = '1' then
|
||||
uart_rx_data_sr(0) <= rx;
|
||||
uart_rx_data_sr(1) <= uart_rx_data_sr(0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process rxd_synchronise;
|
||||
---------------------------------------------------------------------------
|
||||
-- RXD_FILTER
|
||||
-- Filter rxd with a 2 bit counter.
|
||||
---------------------------------------------------------------------------
|
||||
rxd_filter : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_rx_filter <= (others => '1');
|
||||
uart_rx_bit <= '1';
|
||||
else
|
||||
if rx_baud_tick = '1' then
|
||||
-- filter rxd.
|
||||
if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then
|
||||
uart_rx_filter <= uart_rx_filter + 1;
|
||||
elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
|
||||
uart_rx_filter <= uart_rx_filter - 1;
|
||||
end if;
|
||||
-- set the rx bit.
|
||||
if uart_rx_filter = 3 then
|
||||
uart_rx_bit <= '1';
|
||||
elsif uart_rx_filter = 0 then
|
||||
uart_rx_bit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process rxd_filter;
|
||||
---------------------------------------------------------------------------
|
||||
-- RX_BIT_SPACING
|
||||
---------------------------------------------------------------------------
|
||||
rx_bit_spacing : process (clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
uart_rx_bit_tick <= '0';
|
||||
if rx_baud_tick = '1' then
|
||||
if uart_rx_bit_spacing = 15 then
|
||||
uart_rx_bit_tick <= '1';
|
||||
uart_rx_bit_spacing <= (others => '0');
|
||||
else
|
||||
uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
|
||||
end if;
|
||||
if uart_rx_state = rx_get_start_bit then
|
||||
uart_rx_bit_spacing <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process rx_bit_spacing;
|
||||
---------------------------------------------------------------------------
|
||||
-- UART_RECEIVE_DATA
|
||||
---------------------------------------------------------------------------
|
||||
uart_receive_data : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_rx_state <= rx_get_start_bit;
|
||||
uart_rx_data_vec <= (others => '0');
|
||||
uart_rx_count <= (others => '0');
|
||||
uart_rx_data_out_stb <= '0';
|
||||
else
|
||||
uart_rx_data_out_stb <= '0';
|
||||
case uart_rx_state is
|
||||
when rx_get_start_bit =>
|
||||
if rx_baud_tick = '1' and uart_rx_bit = '0' then
|
||||
uart_rx_state <= rx_get_data;
|
||||
end if;
|
||||
when rx_get_data =>
|
||||
if uart_rx_bit_tick = '1' then
|
||||
uart_rx_data_vec(uart_rx_data_vec'high)
|
||||
<= uart_rx_bit;
|
||||
uart_rx_data_vec(
|
||||
uart_rx_data_vec'high-1 downto 0
|
||||
) <= uart_rx_data_vec(
|
||||
uart_rx_data_vec'high downto 1
|
||||
);
|
||||
if uart_rx_count < 7 then
|
||||
uart_rx_count <= uart_rx_count + 1;
|
||||
else
|
||||
uart_rx_count <= (others => '0');
|
||||
uart_rx_state <= rx_get_stop_bit;
|
||||
end if;
|
||||
end if;
|
||||
when rx_get_stop_bit =>
|
||||
if uart_rx_bit_tick = '1' then
|
||||
if uart_rx_bit = '1' then
|
||||
uart_rx_state <= rx_get_start_bit;
|
||||
uart_rx_data_out_stb <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
uart_rx_state <= rx_get_start_bit;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process uart_receive_data;
|
||||
---------------------------------------------------------------------------
|
||||
-- TX_CLOCK_DIVIDER
|
||||
-- Generate baud ticks at the required rate based on the input clock
|
||||
-- frequency and baud rate
|
||||
---------------------------------------------------------------------------
|
||||
tx_clock_divider : process (clock)
|
||||
begin
|
||||
if rising_edge (clock) then
|
||||
if reset = '1' then
|
||||
tx_baud_counter <= 0;
|
||||
tx_baud_tick <= '0';
|
||||
else
|
||||
if tx_baud_counter = c_tx_div - 1 then
|
||||
tx_baud_counter <= 0;
|
||||
tx_baud_tick <= '1';
|
||||
else
|
||||
tx_baud_counter <= tx_baud_counter + 1;
|
||||
tx_baud_tick <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process tx_clock_divider;
|
||||
---------------------------------------------------------------------------
|
||||
-- UART_SEND_DATA
|
||||
-- Get data from data_stream_in and send it one bit at a time upon each
|
||||
-- baud tick. Send data lsb first.
|
||||
-- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1)
|
||||
---------------------------------------------------------------------------
|
||||
uart_send_data : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_tx_data <= '1';
|
||||
uart_tx_data_vec <= (others => '0');
|
||||
uart_tx_count <= (others => '0');
|
||||
uart_tx_state <= tx_send_start_bit;
|
||||
uart_rx_data_in_ack <= '0';
|
||||
uart_rx_data_in_done <= '0';
|
||||
else
|
||||
uart_rx_data_in_ack <= '0';
|
||||
uart_rx_data_in_done <= '0'; --new
|
||||
case uart_tx_state is
|
||||
when tx_send_start_bit =>
|
||||
if tx_baud_tick = '1' and data_stream_in_stb = '1' then
|
||||
uart_tx_data <= '0';
|
||||
uart_tx_state <= tx_send_data;
|
||||
uart_tx_count <= (others => '0');
|
||||
uart_rx_data_in_ack <= '1';
|
||||
uart_tx_data_vec <= data_stream_in;
|
||||
end if;
|
||||
when tx_send_data =>
|
||||
if tx_baud_tick = '1' then
|
||||
uart_tx_data <= uart_tx_data_vec(0);
|
||||
uart_tx_data_vec(
|
||||
uart_tx_data_vec'high-1 downto 0
|
||||
) <= uart_tx_data_vec(
|
||||
uart_tx_data_vec'high downto 1
|
||||
);
|
||||
if uart_tx_count < 7 then
|
||||
uart_tx_count <= uart_tx_count + 1;
|
||||
else
|
||||
uart_tx_count <= (others => '0');
|
||||
uart_tx_state <= tx_send_stop_bit;
|
||||
end if;
|
||||
end if;
|
||||
when tx_send_stop_bit =>
|
||||
if tx_baud_tick = '1' then
|
||||
uart_tx_data <= '1';
|
||||
uart_tx_state <= tx_send_start_bit;
|
||||
uart_rx_data_in_done <= '1'; --new
|
||||
end if;
|
||||
when others =>
|
||||
uart_tx_data <= '1';
|
||||
uart_tx_state <= tx_send_start_bit;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process uart_send_data;
|
||||
end rtl;
|
||||
238
LAB2/src/pak_depak/ipshared/453d/hdl/UART_Manager.vhd
Normal file
238
LAB2/src/pak_depak/ipshared/453d/hdl/UART_Manager.vhd
Normal file
@@ -0,0 +1,238 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Modulo di pi<70> basso livello per la gestione dei dati tra FIFO in e FIFO out ed il --
|
||||
-- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorit<69> <20> data ai dati in --
|
||||
-- arrivo dal PC verso FPGA. --
|
||||
-- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi --
|
||||
-- rischiesti dal 2232H --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity UART_Manager is
|
||||
generic(
|
||||
UART_BAUD_RATE : positive;
|
||||
UART_CLOCK_FREQUENCY : positive --The associated clock frequency
|
||||
);
|
||||
Port (
|
||||
---------Global---------
|
||||
clk_uart : IN STD_LOGIC;
|
||||
reset : IN STD_LOGIC;
|
||||
------------------------
|
||||
|
||||
---------Connessioni comunicazione UART-----------
|
||||
UART_TX : OUT STD_LOGIC;
|
||||
UART_RX : IN STD_LOGIC;
|
||||
---------------------------------------------------
|
||||
|
||||
------------FIFO_DATA_RX (8bit)-------------
|
||||
FIFO_DATA_RX_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_full : IN STD_LOGIC;
|
||||
FIFO_DATA_RX_almost_full : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
------------FIFO_DATA_TX (8bit)-------------
|
||||
--FIFO_DATA_RX_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_empty : IN STD_LOGIC;
|
||||
FIFO_DATA_TX_almost_empty : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end UART_Manager;
|
||||
|
||||
architecture Behavioral of UART_Manager is
|
||||
|
||||
-------------------COMPONENT------------------
|
||||
COMPONENT UART_engine
|
||||
GENERIC(
|
||||
BAUD_RATE : positive;
|
||||
CLOCK_FREQUENCY : positive
|
||||
);
|
||||
PORT(
|
||||
--SYSTEM UART
|
||||
clock : IN std_logic;
|
||||
reset : IN std_logic;
|
||||
|
||||
-- FPGA-->PC
|
||||
data_stream_in : IN std_logic_vector(7 downto 0);
|
||||
data_stream_in_stb : IN std_logic;
|
||||
data_stream_in_ack : OUT std_logic;
|
||||
data_stream_in_done : OUT std_logic;
|
||||
tx : OUT std_logic;
|
||||
|
||||
-- PC-->FPGA
|
||||
data_stream_out : OUT std_logic_vector(7 downto 0);
|
||||
data_stream_out_stb : OUT std_logic;
|
||||
rx : IN std_logic
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
----------------------------------------------
|
||||
|
||||
--------------------SIGNALS-------------------
|
||||
signal state : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00";
|
||||
|
||||
--TX:fromFPGAtoPC
|
||||
signal data_stream_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
|
||||
signal data_stream_in_stb : STD_LOGIC := '0';
|
||||
signal data_stream_in_ack : STD_LOGIC := '0';
|
||||
signal data_stream_in_done : STD_LOGIC := '0';
|
||||
|
||||
signal state_TX : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
|
||||
|
||||
--RX:fromPCtoFPGA
|
||||
signal data_stream_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
|
||||
signal data_stream_out_stb : STD_LOGIC := '0';
|
||||
----------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
Inst_uart: UART_engine
|
||||
GENERIC MAP (
|
||||
BAUD_RATE => UART_BAUD_RATE,
|
||||
CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
|
||||
)
|
||||
PORT MAP(
|
||||
clock => clk_uart,
|
||||
reset => reset,
|
||||
|
||||
-- FPGA-->PC
|
||||
data_stream_in => data_stream_in, --byte FPGA->PC, (in)
|
||||
data_stream_in_stb => data_stream_in_stb, --'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in)
|
||||
data_stream_in_ack => data_stream_in_ack, --'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') <20> stata capita (in)
|
||||
data_stream_in_done => data_stream_in_done, --'1' indica la fine della trasmisione (out)
|
||||
tx => UART_TX,
|
||||
|
||||
-- PC-->FPGA
|
||||
data_stream_out => data_stream_out, --byte PC->FPGA, (out)
|
||||
data_stream_out_stb => data_stream_out_stb, --'1' per 1 clock indica che su data_stream_out c'<27> un nuovo dato (out)
|
||||
-- data_stream_out => FIFO_RX_din,
|
||||
-- data_stream_out_stb => FIFO_RX_wr_en,
|
||||
rx => UART_RX
|
||||
|
||||
);
|
||||
|
||||
fromFPGAtoPC : process(clk_uart, reset)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
state_TX <= x"00";
|
||||
--UART
|
||||
data_stream_in <= (others => '0');
|
||||
data_stream_in_stb <= '0';
|
||||
--FIFO_TX
|
||||
FIFO_DATA_TX_rd_en <= '0';
|
||||
|
||||
elsif rising_edge(clk_uart) then
|
||||
case state_TX is
|
||||
|
||||
when x"FF" =>
|
||||
if(reset = '0') then
|
||||
state_TX <= x"00";
|
||||
else
|
||||
state_TX <= x"FF";
|
||||
end if;
|
||||
--UART
|
||||
data_stream_in <= (others => '0');
|
||||
data_stream_in_stb <= '0';
|
||||
--FIFO_TX
|
||||
FIFO_DATA_TX_rd_en <= '0';
|
||||
|
||||
|
||||
when x"00" =>
|
||||
FIFO_DATA_TX_rd_en <= '0';
|
||||
data_stream_in_stb <= '0';
|
||||
|
||||
if (FIFO_DATA_TX_empty = '0') then --nessun dato da trasmettere al PC
|
||||
state_TX <= x"01"; --si hanno dati in FIFO TX da passare al PC
|
||||
FIFO_DATA_TX_rd_en <= '1'; --abilita lettura FIFO
|
||||
data_stream_in <= FIFO_DATA_TX_dout; --dai alla UART il byte in uscita dalla fifo gi<67> pronto
|
||||
data_stream_in_stb <= '1'; --abilita TX della UART
|
||||
end if;
|
||||
|
||||
|
||||
when x"01" =>
|
||||
FIFO_DATA_TX_rd_en <= '0'; --blocca la lettura FIFO
|
||||
--tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0'
|
||||
if (data_stream_in_ack = '1') then
|
||||
state_TX <= x"02";
|
||||
data_stream_in_stb <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
when x"02" =>
|
||||
-- data_stream_in_done = '1' significa fin trasmisisone UART
|
||||
if (data_stream_in_done = '1') then
|
||||
state_TX <= x"00";
|
||||
end if;
|
||||
|
||||
|
||||
when others =>
|
||||
state_TX <= x"00";
|
||||
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
fromPCtoFPGA : process(clk_uart, reset)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
FIFO_DATA_RX_din <= (others => '0');
|
||||
FIFO_DATA_RX_wr_en <= '0';
|
||||
|
||||
elsif rising_edge(clk_uart) then
|
||||
FIFO_DATA_RX_wr_en <= '0';
|
||||
if (data_stream_out_stb = '1') then --arrivato nuovo dato sulla UART, caricalo in FIGO RX
|
||||
FIFO_DATA_RX_wr_en <= '1';
|
||||
FIFO_DATA_RX_din <= data_stream_out;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------ASSIGMENT------------------
|
||||
FIFO_DATA_RX_clk <= clk_uart;
|
||||
FIFO_DATA_TX_clk <= clk_uart;
|
||||
|
||||
FIFO_DATA_RX_rst <= reset;
|
||||
-----------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
Reference in New Issue
Block a user