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Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality

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Davide Cavagnola
2025-05-16 16:44:46 +02:00
parent 55c5c84247
commit 460378cdaa
1 changed files with 1 additions and 1 deletions
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LAB3/src/digilent_jstk2.vhd
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@@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
ENTITY digilent_jstk2 IS ENTITY digilent_jstk2 IS
GENERIC ( GENERIC (
DELAY_US : INTEGER := 100; -- Delay (in us) between two packets DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz) CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz) SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
); );