PickleRick/DESD
1
0
Fork 0
Code Issues 2 Pull Requests Releases Activity

third commit

Browse Source
This commit is contained in:
Davide Cavagnola
2025-03-18 00:10:07 +01:00
parent a73750948c
commit 4bb43837f8
55 changed files with 5454 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.Vivado_Implementation.queue.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="david" Host="DAVIDE-SAMSUNG" Pid="8676">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.init_design.end.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="david" Host="DAVIDE-SAMSUNG" Pid="8676">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.opt_design.end.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="david" Host="DAVIDE-SAMSUNG" Pid="8676">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.phys_opt_design.end.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="david" Host="DAVIDE-SAMSUNG" Pid="8676">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.place_design.end.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="david" Host="DAVIDE-SAMSUNG" Pid="8676">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.route_design.end.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="david" Host="DAVIDE-SAMSUNG" Pid="12972" HostCore="8" HostMemory="08258056192">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.vivado.end.rst Normal file
View File

5
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.begin.rst Normal file
View File

@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="david" Host="DAVIDE-SAMSUNG" Pid="8676">
</Process>
</ProcessHandle>

0
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/.write_bitstream.end.rst Normal file
View File

270
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.js Normal file
View File

@@ -0,0 +1,270 @@
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}

67
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/ISEWrap.sh Normal file
View File

@@ -0,0 +1,67 @@
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL

15
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_bus_skew_routed.rpt Normal file
View File

@@ -0,0 +1,15 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:47 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file KittCar_bus_skew_routed.rpt -pb KittCar_bus_skew_routed.pb -rpx KittCar_bus_skew_routed.rpx
| Design : KittCar
| Device : 7a35t-cpg236
| Speed File : -1 PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

146
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_clock_utilization_routed.rpt Normal file
View File

@@ -0,0 +1,146 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:47 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_clock_utilization -file KittCar_clock_utilization_routed.rpt
| Design : KittCar
| Device : 7a35t-cpg236
| Speed File : -1 PRODUCTION 1.23 2018-06-13
| Design State : Routed
-------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y0
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 20 | 0 | 0 | 0 |
| BUFMR | 0 | 10 | 0 | 0 | 0 |
| BUFR | 0 | 20 | 0 | 0 | 0 |
| MMCM | 0 | 5 | 0 | 0 | 0 |
| PLL | 0 | 5 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 64 | 0 | 10.000 | sys_clk_pin | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | IOB_X1Y26 | IOB_X1Y26 | X1Y0 | 1 | 0 | 10.000 | sys_clk_pin | clk_IBUF_inst/O | clk_IBUF |
+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 64 | 1200 | 53 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 1 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | sys_clk_pin | 10.000 | {0.000 5.000} | 64 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+-----+----+-----------------------+
| | X0 | X1 | HORIZONTAL PROG DELAY |
+----+-----+----+-----------------------+
| Y2 | 0 | 0 | 0 |
| Y1 | 0 | 0 | 0 |
| Y0 | 64 | 0 | 0 |
+----+-----+----+-----------------------+
7. Clock Region Cell Placement per Global Clock: Region X0Y0
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 64 | 0 | 64 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X1Y26 [get_ports clk]
# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock {CLKAG_clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup

81
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_control_sets_placed.rpt Normal file
View File

@@ -0,0 +1,81 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:34 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_control_sets -verbose -file KittCar_control_sets_placed.rpt
| Design : KittCar
| Device : xc7a35t
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Total control sets | 3 |
| Minimum number of control sets | 3 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 7 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
2. Histogram
------------
+--------------------+-------+
| Fanout | Count |
+--------------------+-------+
| Total control sets | 3 |
| >= 0 to < 4 | 1 |
| >= 4 to < 6 | 0 |
| >= 6 to < 8 | 0 |
| >= 8 to < 10 | 0 |
| >= 10 to < 12 | 0 |
| >= 12 to < 14 | 0 |
| >= 14 to < 16 | 0 |
| >= 16 | 2 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 0 | 0 |
| No | No | Yes | 48 | 12 |
| No | Yes | No | 1 | 1 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 16 | 7 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+-----------------+---------------+------------------+------------------+----------------+--------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
+-----------------+---------------+------------------+------------------+----------------+--------------+
| up_reg_i_2_n_0 | | reset_IBUF | 1 | 1 | 1.00 |
| clk_IBUF_BUFG | leds_sr0 | reset_IBUF | 7 | 16 | 2.29 |
| clk_IBUF_BUFG | | reset_IBUF | 12 | 48 | 4.00 |
+-----------------+---------------+------------------+------------------+----------------+--------------+

67
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_opted.rpt Normal file
View File

@@ -0,0 +1,67 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:32 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_drc -file KittCar_drc_opted.rpt -pb KittCar_drc_opted.pb -rpx KittCar_drc_opted.rpx
| Design : KittCar
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 4
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| DPIP-1 | Warning | Input pipelining | 1 |
| DPOP-1 | Warning | PREG Output pipelining | 1 |
| DPOP-2 | Warning | MREG Output pipelining | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
DPIP-1#1 Warning
Input pipelining
DSP counter2 input counter2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPOP-1#1 Warning
PREG Output pipelining
DSP counter2 output counter2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-2#1 Warning
MREG Output pipelining
DSP counter2 multiplier stage counter2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

73
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_drc_routed.rpt Normal file
View File

@@ -0,0 +1,73 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:46 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_drc -file KittCar_drc_routed.rpt -pb KittCar_drc_routed.pb -rpx KittCar_drc_routed.rpx
| Design : KittCar
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Fully Routed
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 5
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| DPIP-1 | Warning | Input pipelining | 1 |
| DPOP-1 | Warning | PREG Output pipelining | 1 |
| DPOP-2 | Warning | MREG Output pipelining | 1 |
| PDRC-153 | Warning | Gated clock check | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
DPIP-1#1 Warning
Input pipelining
DSP counter2 input counter2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
Related violations: <none>
DPOP-1#1 Warning
PREG Output pipelining
DSP counter2 output counter2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>
DPOP-2#1 Warning
MREG Output pipelining
DSP counter2 multiplier stage counter2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>
PDRC-153#1 Warning
Gated clock check
Net up_reg_i_2_n_0 is a gated clock net sourced by a combinational pin up_reg_i_2/O, cell up_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
Related violations: <none>

280
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_io_placed.rpt Normal file
View File

@@ -0,0 +1,280 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:34 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_io -file KittCar_io_placed.rpt
| Design : KittCar
| Device : xc7a35t
| Speed File : -1
| Package : cpg236
| Package Version : FINAL 2014-02-19
| Package Pin Delay Version : VERS. 2.0 2014-02-19
-------------------------------------------------------------------------------------------------
IO Information
Table of Contents
-----------------
1. Summary
2. IO Assignments by Package Pin
1. Summary
----------
+---------------+
| Total User IO |
+---------------+
| 34 |
+---------------+
2. IO Assignments by Package Pin
--------------------------------
+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | |
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | |
| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | |
| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | |
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | |
| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | |
| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | |
| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | |
| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | |
| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| E19 | led[1] | High Range | IO_L3N_T0_DQS_EMCCLK_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | |
| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | |
| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
| L1 | led[15] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
| N3 | led[13] | High Range | IO_L12P_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
| P1 | led[14] | High Range | IO_L19N_T3_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| P3 | led[12] | High Range | IO_L12N_T1_MRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| R2 | sw[15] | High Range | IO_L1P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R3 | sw[11] | High Range | IO_L2P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
| T1 | sw[14] | High Range | IO_L3P_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T2 | sw[10] | High Range | IO_L1N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T3 | sw[9] | High Range | IO_L2N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U1 | sw[13] | High Range | IO_L3N_T0_DQS_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| U2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
| U3 | led[11] | High Range | IO_L9P_T1_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U5 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
| U8 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | |
| U14 | led[6] | High Range | IO_25_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U15 | led[5] | High Range | IO_L23P_T3_A03_D19_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U16 | led[0] | High Range | IO_L23N_T3_A02_D18_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
| U18 | reset | High Range | IO_L18N_T2_A11_D27_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| U19 | led[2] | High Range | IO_L15P_T2_DQS_RDWR_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| V2 | sw[8] | High Range | IO_L5P_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| V3 | led[9] | High Range | IO_L6P_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
| V8 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
| V13 | led[8] | High Range | IO_L24P_T3_A01_D17_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V14 | led[7] | High Range | IO_L24N_T3_A00_D16_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| V15 | sw[5] | High Range | IO_L21P_T3_DQS_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| V16 | sw[1] | High Range | IO_L19P_T3_A10_D26_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| V17 | sw[0] | High Range | IO_L19N_T3_A09_D25_VREF_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| V19 | led[3] | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W2 | sw[12] | High Range | IO_L5N_T0_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| W3 | led[10] | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W5 | clk | High Range | IO_L12P_T1_MRCC_34 | INPUT | LVCMOS33 | 34 | | | | NONE | | FIXED | | | | NONE | | | |
| W6 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W7 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
| W13 | sw[7] | High Range | IO_L22P_T3_A05_D21_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| W14 | sw[6] | High Range | IO_L22N_T3_A04_D20_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| W15 | sw[4] | High Range | IO_L21N_T3_DQS_A06_D22_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| W16 | sw[2] | High Range | IO_L20P_T3_A08_D24_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| W17 | sw[3] | High Range | IO_L20N_T3_A07_D23_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | |
| W18 | led[4] | High Range | IO_L16P_T2_CSI_B_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
* Default value
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.

206
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_methodology_drc_routed.rpt Normal file
View File

@@ -0,0 +1,206 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:46 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_methodology -file KittCar_methodology_drc_routed.rpt -pb KittCar_methodology_drc_routed.pb -rpx KittCar_methodology_drc_routed.rpx
| Design : KittCar
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Fully Routed
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Report Methodology
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Max violations: <unlimited>
Violations found: 34
+-----------+----------+-------------------------------+------------+
| Rule | Severity | Description | Violations |
+-----------+----------+-------------------------------+------------+
| TIMING-18 | Warning | Missing input or output delay | 33 |
| TIMING-20 | Warning | Non-clocked latch | 1 |
+-----------+----------+-------------------------------+------------+
2. REPORT DETAILS
-----------------
TIMING-18#1 Warning
Missing input or output delay
An input delay is missing on reset relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#2 Warning
Missing input or output delay
An input delay is missing on sw[0] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#3 Warning
Missing input or output delay
An input delay is missing on sw[10] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#4 Warning
Missing input or output delay
An input delay is missing on sw[11] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#5 Warning
Missing input or output delay
An input delay is missing on sw[12] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#6 Warning
Missing input or output delay
An input delay is missing on sw[13] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#7 Warning
Missing input or output delay
An input delay is missing on sw[14] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#8 Warning
Missing input or output delay
An input delay is missing on sw[15] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#9 Warning
Missing input or output delay
An input delay is missing on sw[1] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#10 Warning
Missing input or output delay
An input delay is missing on sw[2] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#11 Warning
Missing input or output delay
An input delay is missing on sw[3] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#12 Warning
Missing input or output delay
An input delay is missing on sw[4] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#13 Warning
Missing input or output delay
An input delay is missing on sw[5] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#14 Warning
Missing input or output delay
An input delay is missing on sw[6] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#15 Warning
Missing input or output delay
An input delay is missing on sw[7] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#16 Warning
Missing input or output delay
An input delay is missing on sw[8] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#17 Warning
Missing input or output delay
An input delay is missing on sw[9] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#18 Warning
Missing input or output delay
An output delay is missing on led[0] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#19 Warning
Missing input or output delay
An output delay is missing on led[10] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#20 Warning
Missing input or output delay
An output delay is missing on led[11] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#21 Warning
Missing input or output delay
An output delay is missing on led[12] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#22 Warning
Missing input or output delay
An output delay is missing on led[13] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#23 Warning
Missing input or output delay
An output delay is missing on led[14] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#24 Warning
Missing input or output delay
An output delay is missing on led[15] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#25 Warning
Missing input or output delay
An output delay is missing on led[1] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#26 Warning
Missing input or output delay
An output delay is missing on led[2] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#27 Warning
Missing input or output delay
An output delay is missing on led[3] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#28 Warning
Missing input or output delay
An output delay is missing on led[4] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#29 Warning
Missing input or output delay
An output delay is missing on led[5] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#30 Warning
Missing input or output delay
An output delay is missing on led[6] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#31 Warning
Missing input or output delay
An output delay is missing on led[7] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#32 Warning
Missing input or output delay
An output delay is missing on led[8] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-18#33 Warning
Missing input or output delay
An output delay is missing on led[9] relative to clock(s) sys_clk_pin
Related violations: <none>
TIMING-20#1 Warning
Non-clocked latch
The latch up_reg cannot be properly analyzed as its control pin up_reg/G is not reached by a timing clock
Related violations: <none>

147
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_power_routed.rpt Normal file
View File

@@ -0,0 +1,147 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:47 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_power -file KittCar_power_routed.rpt -pb KittCar_power_summary_routed.pb -rpx KittCar_power_routed.rpx
| Design : KittCar
| Device : xc7a35tcpg236-1
| Design State : routed
| Grade : commercial
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.075 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.003 |
| Device Static (W) | 0.072 |
| Effective TJA (C/W) | 5.0 |
| Max Ambient (C) | 84.6 |
| Junction Temperature (C) | 25.4 |
| Confidence Level | Low |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks | <0.001 | 3 | --- | --- |
| Slice Logic | <0.001 | 212 | --- | --- |
| LUT as Logic | <0.001 | 93 | 20800 | 0.45 |
| CARRY4 | <0.001 | 22 | 8150 | 0.27 |
| Register | <0.001 | 65 | 41600 | 0.16 |
| Others | 0.000 | 4 | --- | --- |
| Signals | <0.001 | 158 | --- | --- |
| DSPs | <0.001 | 1 | 90 | 1.11 |
| I/O | <0.001 | 34 | 106 | 32.08 |
| Static Power | 0.072 | | | |
| Total | 0.075 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.012 | 0.003 | 0.010 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.013 | 0.000 | 0.013 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Low | | |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 5.0 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 4.6 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------------+--------+-----------------+
| sys_clk_pin | clk | 10.0 |
+-------------+--------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+---------+-----------+
| Name | Power (W) |
+---------+-----------+
| KittCar | 0.003 |
+---------+-----------+

11
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_route_status.rpt Normal file
View File

@@ -0,0 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 357 :
# of nets not needing routing.......... : 195 :
# of internally routed nets........ : 195 :
# of routable nets..................... : 162 :
# of fully routed nets............. : 162 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

1861
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_timing_summary_routed.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

212
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/KittCar_utilization_placed.rpt Normal file
View File

@@ -0,0 +1,212 @@
Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
| Date : Mon Mar 17 20:34:34 2025
| Host : Davide-Samsung running 64-bit major release (build 9200)
| Command : report_utilization -file KittCar_utilization_placed.rpt -pb KittCar_utilization_placed.pb
| Design : KittCar
| Device : 7a35tcpg236-1
| Design State : Fully Placed
-----------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs | 93 | 0 | 20800 | 0.45 |
| LUT as Logic | 93 | 0 | 20800 | 0.45 |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 65 | 0 | 41600 | 0.16 |
| Register as Flip Flop | 64 | 0 | 41600 | 0.15 |
| Register as Latch | 1 | 0 | 41600 | <0.01 |
| F7 Muxes | 0 | 0 | 16300 | 0.00 |
| F8 Muxes | 0 | 0 | 8150 | 0.00 |
+-------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 1 | Yes | - | Set |
| 64 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 0 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+--------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------------------------------------+------+-------+-----------+-------+
| Slice | 31 | 0 | 8150 | 0.38 |
| SLICEL | 12 | 0 | | |
| SLICEM | 19 | 0 | | |
| LUT as Logic | 93 | 0 | 20800 | 0.45 |
| using O5 output only | 0 | | | |
| using O6 output only | 65 | | | |
| using O5 and O6 | 28 | | | |
| LUT as Memory | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| Slice Registers | 65 | 0 | 41600 | 0.16 |
| Register driven from within the Slice | 63 | | | |
| Register driven from outside the Slice | 2 | | | |
| LUT in front of the register is unused | 0 | | | |
| LUT in front of the register is used | 2 | | | |
| Unique Control Sets | 3 | | 8150 | 0.04 |
+--------------------------------------------+------+-------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 50 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 |
| RAMB18 | 0 | 0 | 100 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 1 | 0 | 90 | 1.11 |
| DSP48E1 only | 1 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 34 | 34 | 106 | 32.08 |
| IOB Master Pads | 16 | | | |
| IOB Slave Pads | 17 | | | |
| Bonded IPADs | 0 | 0 | 10 | 0.00 |
| Bonded OPADs | 0 | 0 | 4 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 0 | 0 | 5 | 0.00 |
| IBUFDS | 0 | 0 | 104 | 0.00 |
| GTPE2_CHANNEL | 0 | 0 | 2 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 250 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 |
| ILOGIC | 0 | 0 | 106 | 0.00 |
| OLOGIC | 0 | 0 | 106 | 0.00 |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 20 | 0.00 |
| MMCME2_ADV | 0 | 0 | 5 | 0.00 |
| PLLE2_ADV | 0 | 0 | 5 | 0.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 72 | 0.00 |
| BUFR | 0 | 0 | 20 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 64 | Flop & Latch |
| LUT2 | 51 | LUT |
| LUT4 | 32 | LUT |
| CARRY4 | 22 | CarryLogic |
| IBUF | 18 | IO |
| OBUF | 16 | IO |
| LUT3 | 16 | LUT |
| LUT6 | 15 | LUT |
| LUT5 | 4 | LUT |
| LUT1 | 3 | LUT |
| LDPE | 1 | Flop & Latch |
| DSP48E1 | 1 | Block Arithmetic |
| BUFG | 1 | Clock |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+

9
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/htr.txt Normal file
View File

@@ -0,0 +1,9 @@
REM
REM Vivado(TM)
REM htr.txt: a Vivado-generated description of how-to-repeat the
REM the basic steps of a run. Note that runme.bat/sh needs
REM to be invoked for Vivado to track run status.
REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
REM
vivado -log KittCar.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source KittCar.tcl -notrace

31
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/project.wdf Normal file
View File

@@ -0,0 +1,31 @@
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6635356365666130633361663437363461656435356437643038343135393562:506172656e742050412070726f6a656374204944:00
eof:3337883414

40
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/rundef.js Normal file
View File

@@ -0,0 +1,40 @@
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2020.2/bin;";
} else {
PathVal = "C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2020.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
// pre-commands:
ISETouchFile( "init_design", "begin" );
ISEStep( "vivado",
"-log KittCar.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source KittCar.tcl -notrace" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}

10
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.bat Normal file
View File

@@ -0,0 +1,10 @@
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

47
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/runme.sh Normal file
View File

@@ -0,0 +1,47 @@
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
#
echo "This script was generated under a different operating system."
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
exit
if [ -z "$PATH" ]; then
PATH=C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2020.2/bin
else
PATH=C:/Xilinx/Vivado/2020.2/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2020.2/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2020.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='C:/DESD/LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
# pre-commands:
/bin/touch .init_design.begin.rst
EAStep vivado -log KittCar.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source KittCar.tcl -notrace

745
LAB1/lab1_kit_car/lab1_kit_car.runs/impl_1/usage_statistics_webtalk.html Normal file
View File

@@ -0,0 +1,745 @@
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>3064766</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar 17 20:34:53 2025</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2020.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>f55cefa0c3af4764aed55d7d0841595b</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>22</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>883cc468a2bd5c84ae5bff6c9bd19760</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>883cc468a2bd5c84ae5bff6c9bd19760</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>13th Gen Intel(R) Core(TM) i3-1315U</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release (build 9200)</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>8.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>abstractfileview_reload=1</TD>
<TD>addsrcwizard_specify_hdl_netlist_block_design=1</TD>
<TD>addsrcwizard_specify_or_create_constraint_files=2</TD>
<TD>basedialog_apply=2</TD>
</TR><TR ALIGN='LEFT'> <TD>basedialog_cancel=4</TD>
<TD>basedialog_no=1</TD>
<TD>basedialog_ok=93</TD>
<TD>basedialog_yes=25</TD>
</TR><TR ALIGN='LEFT'> <TD>boardchooser_board_table=6</TD>
<TD>cmdmsgdialog_ok=5</TD>
<TD>constraintschooserpanel_add_files=1</TD>
<TD>createsrcfiledialog_file_name=2</TD>
</TR><TR ALIGN='LEFT'> <TD>filesetpanel_file_set_panel_tree=37</TD>
<TD>flownavigatortreepanel_flow_navigator_tree=76</TD>
<TD>fpgachooser_fpga_table=1</TD>
<TD>gettingstartedview_create_new_project=1</TD>
</TR><TR ALIGN='LEFT'> <TD>gettingstartedview_open_project=1</TD>
<TD>hjfilechooserhelpers_jump_to_downloads_directory=2</TD>
<TD>hjfilechooserhelpers_refresh_folder_view_to_reflect_external=1</TD>
<TD>hjfilechooserrecentlistpreview_recent_directories=1</TD>
</TR><TR ALIGN='LEFT'> <TD>logmonitor_monitor=2</TD>
<TD>mainmenumgr_help=2</TD>
<TD>mainmenumgr_reports=4</TD>
<TD>mainmenumgr_tools=6</TD>
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_view=9</TD>
<TD>mainmenumgr_window=12</TD>
<TD>maintoolbarmgr_run=3</TD>
<TD>mainwinmenumgr_layout=32</TD>
</TR><TR ALIGN='LEFT'> <TD>mainwinmenumgr_load=5</TD>
<TD>msgtreepanel_message_view_tree=7</TD>
<TD>numjobschooser_number_of_jobs=2</TD>
<TD>packagetreepanel_package_tree_panel=10</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_add_sources=2</TD>
<TD>pacommandnames_auto_connect_target=2</TD>
<TD>pacommandnames_auto_update_hier=4</TD>
<TD>pacommandnames_run_bitgen=20</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_src_replace_file=1</TD>
<TD>paviews_code=12</TD>
<TD>paviews_device=2</TD>
<TD>paviews_project_summary=17</TD>
</TR><TR ALIGN='LEFT'> <TD>programdebugtab_open_target=2</TD>
<TD>programdebugtab_program_device=19</TD>
<TD>programdebugtab_refresh_device=5</TD>
<TD>programfpgadialog_program=30</TD>
</TR><TR ALIGN='LEFT'> <TD>programfpgadialog_specify_bitstream_file=2</TD>
<TD>progressdialog_background=1</TD>
<TD>projectnamechooser_choose_project_location=1</TD>
<TD>projectnamechooser_project_name=2</TD>
</TR><TR ALIGN='LEFT'> <TD>projecttab_close_design=1</TD>
<TD>projecttab_reload=4</TD>
<TD>rdicommands_custom_commands=3</TD>
<TD>rdicommands_delete=1</TD>
</TR><TR ALIGN='LEFT'> <TD>rungadget_show_warning_and_error_messages_in_messages=1</TD>
<TD>searchcommandcomponent_quick_access=2</TD>
<TD>settingsdialog_project_tree=1</TD>
<TD>settingsprojectgeneralpage_choose_device_for_your_project=1</TD>
</TR><TR ALIGN='LEFT'> <TD>signaltreepanel_signal_tree_table=12</TD>
<TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1</TD>
<TD>srcchooserpanel_create_file=1</TD>
<TD>srcchoosertable_src_chooser_table=2</TD>
</TR><TR ALIGN='LEFT'> <TD>srcmenu_ip_hierarchy=3</TD>
<TD>syntheticagettingstartedview_recent_projects=1</TD>
<TD>syntheticastatemonitor_cancel=1</TD>
<TD>touchpointsurveydialog_no=1</TD>
</TR><TR ALIGN='LEFT'> <TD>touchpointsurveydialog_remind_me_later=1</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>addsources=2</TD>
<TD>autoconnecttarget=2</TD>
<TD>editdelete=1</TD>
<TD>exitapp=2</TD>
</TR><TR ALIGN='LEFT'> <TD>fliptoviewtaskimplementation=1</TD>
<TD>fliptoviewtasksynthesis=1</TD>
<TD>launchprogramfpga=32</TD>
<TD>newproject=1</TD>
</TR><TR ALIGN='LEFT'> <TD>openhardwaremanager=15</TD>
<TD>openproject=1</TD>
<TD>openrecenttarget=2</TD>
<TD>programdevice=15</TD>
</TR><TR ALIGN='LEFT'> <TD>refreshdevice=5</TD>
<TD>runbitgen=32</TD>
<TD>runimplementation=5</TD>
<TD>runschematic=2</TD>
</TR><TR ALIGN='LEFT'> <TD>runsynthesis=9</TD>
<TD>savedesign=1</TD>
<TD>showview=30</TD>
<TD>timingconstraintswizard=1</TD>
</TR><TR ALIGN='LEFT'> <TD>toolssettings=5</TD>
<TD>updatesourcefiles=1</TD>
<TD>viewlayoutcmd=5</TD>
<TD>viewtaskimplementation=7</TD>
</TR><TR ALIGN='LEFT'> <TD>viewtaskprogramanddebug=1</TD>
<TD>viewtaskprojectmanager=8</TD>
<TD>viewtasksynthesis=1</TD>
</TR> </TABLE>
</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>guimode=3</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
<TD>core_container=false</TD>
<TD>currentimplrun=impl_1</TD>
<TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
<TD>designmode=RTL</TD>
<TD>export_simulation_activehdl=0</TD>
<TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
<TD>export_simulation_questa=0</TD>
<TD>export_simulation_riviera=0</TD>
<TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
<TD>implstrategy=Vivado Implementation Defaults</TD>
<TD>launch_simulation_activehdl=0</TD>
<TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
<TD>launch_simulation_questa=0</TD>
<TD>launch_simulation_riviera=0</TD>
<TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=0</TD>
<TD>simulator_language=Mixed</TD>
<TD>srcsetcount=1</TD>
<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
<TD>target_simulator=XSim</TD>
<TD>totalimplruns=1</TD>
<TD>totalsynthesisruns=1</TD>
</TR> </TABLE>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=1</TD>
<TD>carry4=22</TD>
<TD>dsp48e1=1</TD>
<TD>fdce=64</TD>
</TR><TR ALIGN='LEFT'> <TD>gnd=2</TD>
<TD>ibuf=18</TD>
<TD>ldpe=1</TD>
<TD>lut1=3</TD>
</TR><TR ALIGN='LEFT'> <TD>lut2=51</TD>
<TD>lut3=16</TD>
<TD>lut4=32</TD>
<TD>lut5=4</TD>
</TR><TR ALIGN='LEFT'> <TD>lut6=15</TD>
<TD>obuf=16</TD>
<TD>vcc=2</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=1</TD>
<TD>carry4=22</TD>
<TD>dsp48e1=1</TD>
<TD>fdce=64</TD>
</TR><TR ALIGN='LEFT'> <TD>gnd=2</TD>
<TD>ibuf=18</TD>
<TD>ldpe=1</TD>
<TD>lut1=3</TD>
</TR><TR ALIGN='LEFT'> <TD>lut2=51</TD>
<TD>lut3=16</TD>
<TD>lut4=32</TD>
<TD>lut5=4</TD>
</TR><TR ALIGN='LEFT'> <TD>lut6=15</TD>
<TD>obuf=16</TD>
<TD>vcc=2</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-aggressive_hold_fix=default::[not_specified]</TD>
<TD>-bram_register_opt=default::[not_specified]</TD>
<TD>-clock_opt=default::[not_specified]</TD>
<TD>-critical_cell_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-critical_pin_opt=default::[not_specified]</TD>
<TD>-directive=default::[not_specified]</TD>
<TD>-dsp_register_opt=default::[not_specified]</TD>
<TD>-effort_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-fanout_opt=default::[not_specified]</TD>
<TD>-hold_fix=default::[not_specified]</TD>
<TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
<TD>-multi_clock_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-placement_opt=default::[not_specified]</TD>
<TD>-restruct_opt=default::[not_specified]</TD>
<TD>-retime=default::[not_specified]</TD>
<TD>-rewire=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-shift_register_opt=default::[not_specified]</TD>
<TD>-uram_register_opt=default::[not_specified]</TD>
<TD>-verbose=default::[not_specified]</TD>
<TD>-vhfn=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
<TD>-checks=default::[not_specified]</TD>
<TD>-fail_on=default::[not_specified]</TD>
<TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
<TD>-internal=default::[not_specified]</TD>
<TD>-internal_only=default::[not_specified]</TD>
<TD>-max_msgs_per_check=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-messages=default::[not_specified]</TD>
<TD>-name=default::[not_specified]</TD>
<TD>-no_waivers=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-ruledecks=default::[not_specified]</TD>
<TD>-upgrade_cw=default::[not_specified]</TD>
<TD>-waived=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'> <TD>cfgbvs-1=1</TD>
<TD>dpip-1=1</TD>
<TD>dpop-1=1</TD>
<TD>dpop-2=1</TD>
</TR><TR ALIGN='LEFT'> <TD>pdrc-153=1</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
<TD>-checks=default::[not_specified]</TD>
<TD>-fail_on=default::[not_specified]</TD>
<TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
<TD>-messages=default::[not_specified]</TD>
<TD>-name=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-slack_lesser_than=default::[not_specified]</TD>
<TD>-waived=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'> <TD>timing-18=33</TD>
<TD>timing-20=1</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-advisory=default::[not_specified]</TD>
<TD>-append=default::[not_specified]</TD>
<TD>-file=[specified]</TD>
<TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'> <TD>-hier=default::power</TD>
<TD>-hierarchical_depth=default::4</TD>
<TD>-l=default::[not_specified]</TD>
<TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-no_propagation=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
<TD>-rpx=[specified]</TD>
<TD>-verbose=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-vid=default::[not_specified]</TD>
<TD>-xpe=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>airflow=250 (LFM)</TD>
<TD>ambient_temp=25.0 (C)</TD>
<TD>bi-dir_toggle=12.500000</TD>
<TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>board_layers=12to15 (12 to 15 Layers)</TD>
<TD>board_selection=medium (10&quot;x10&quot;)</TD>
<TD>clocks=0.000880</TD>
<TD>confidence_level_clock_activity=High</TD>
</TR><TR ALIGN='LEFT'> <TD>confidence_level_design_state=High</TD>
<TD>confidence_level_device_models=High</TD>
<TD>confidence_level_internal_activity=Medium</TD>
<TD>confidence_level_io_activity=Low</TD>
</TR><TR ALIGN='LEFT'> <TD>confidence_level_overall=Low</TD>
<TD>customer=TBD</TD>
<TD>customer_class=TBD</TD>
<TD>devstatic=0.071708</TD>
</TR><TR ALIGN='LEFT'> <TD>die=xc7a35tcpg236-1</TD>
<TD>dsp=0.000751</TD>
<TD>dsp_output_toggle=12.500000</TD>
<TD>dynamic=0.003182</TD>
</TR><TR ALIGN='LEFT'> <TD>effective_thetaja=5.00</TD>
<TD>enable_probability=0.990000</TD>
<TD>family=artix7</TD>
<TD>ff_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'> <TD>flow_state=routed</TD>
<TD>heatsink=medium (Medium Profile)</TD>
<TD>i/o=0.000582</TD>
<TD>input_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'> <TD>junction_temp=25.4 (C)</TD>
<TD>logic=0.000562</TD>
<TD>mgtavcc_dynamic_current=0.000000</TD>
<TD>mgtavcc_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>mgtavcc_total_current=0.000000</TD>
<TD>mgtavcc_voltage=1.000000</TD>
<TD>mgtavtt_dynamic_current=0.000000</TD>
<TD>mgtavtt_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>mgtavtt_total_current=0.000000</TD>
<TD>mgtavtt_voltage=1.200000</TD>
<TD>netlist_net_matched=NA</TD>
<TD>off-chip_power=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>on-chip_power=0.074889</TD>
<TD>output_enable=1.000000</TD>
<TD>output_load=5.000000</TD>
<TD>output_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'> <TD>package=cpg236</TD>
<TD>pct_clock_constrained=0.000000</TD>
<TD>pct_inputs_defined=5</TD>
<TD>platform=nt64</TD>
</TR><TR ALIGN='LEFT'> <TD>process=typical</TD>
<TD>ram_enable=50.000000</TD>
<TD>ram_write=50.000000</TD>
<TD>read_saif=False</TD>
</TR><TR ALIGN='LEFT'> <TD>set/reset_probability=0.000000</TD>
<TD>signal_rate=False</TD>
<TD>signals=0.000407</TD>
<TD>simulation_file=None</TD>
</TR><TR ALIGN='LEFT'> <TD>speedgrade=-1</TD>
<TD>static_prob=False</TD>
<TD>temp_grade=commercial</TD>
<TD>thetajb=7.5 (C/W)</TD>
</TR><TR ALIGN='LEFT'> <TD>thetasa=4.6 (C/W)</TD>
<TD>toggle_rate=False</TD>
<TD>user_board_temp=25.0 (C)</TD>
<TD>user_effective_thetaja=5.00</TD>
</TR><TR ALIGN='LEFT'> <TD>user_junc_temp=25.4 (C)</TD>
<TD>user_thetajb=7.5 (C/W)</TD>
<TD>user_thetasa=4.6 (C/W)</TD>
<TD>vccadc_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vccadc_static_current=0.020000</TD>
<TD>vccadc_total_current=0.020000</TD>
<TD>vccadc_voltage=1.800000</TD>
<TD>vccaux_dynamic_current=0.000017</TD>
</TR><TR ALIGN='LEFT'> <TD>vccaux_io_dynamic_current=0.000000</TD>
<TD>vccaux_io_static_current=0.000000</TD>
<TD>vccaux_io_total_current=0.000000</TD>
<TD>vccaux_io_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'> <TD>vccaux_static_current=0.012615</TD>
<TD>vccaux_total_current=0.012632</TD>
<TD>vccaux_voltage=1.800000</TD>
<TD>vccbram_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vccbram_static_current=0.000161</TD>
<TD>vccbram_total_current=0.000161</TD>
<TD>vccbram_voltage=1.000000</TD>
<TD>vccint_dynamic_current=0.002727</TD>
</TR><TR ALIGN='LEFT'> <TD>vccint_static_current=0.009539</TD>
<TD>vccint_total_current=0.012266</TD>
<TD>vccint_voltage=1.000000</TD>
<TD>vcco12_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco12_static_current=0.000000</TD>
<TD>vcco12_total_current=0.000000</TD>
<TD>vcco12_voltage=1.200000</TD>
<TD>vcco135_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco135_static_current=0.000000</TD>
<TD>vcco135_total_current=0.000000</TD>
<TD>vcco135_voltage=1.350000</TD>
<TD>vcco15_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco15_static_current=0.000000</TD>
<TD>vcco15_total_current=0.000000</TD>
<TD>vcco15_voltage=1.500000</TD>
<TD>vcco18_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco18_static_current=0.000000</TD>
<TD>vcco18_total_current=0.000000</TD>
<TD>vcco18_voltage=1.800000</TD>
<TD>vcco25_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco25_static_current=0.000000</TD>
<TD>vcco25_total_current=0.000000</TD>
<TD>vcco25_voltage=2.500000</TD>
<TD>vcco33_dynamic_current=0.000129</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco33_static_current=0.001000</TD>
<TD>vcco33_total_current=0.001129</TD>
<TD>vcco33_voltage=3.300000</TD>
<TD>version=2020.2</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
<TD>bufgctrl_fixed=0</TD>
<TD>bufgctrl_used=1</TD>
<TD>bufgctrl_util_percentage=3.13</TD>
</TR><TR ALIGN='LEFT'> <TD>bufhce_available=72</TD>
<TD>bufhce_fixed=0</TD>
<TD>bufhce_used=0</TD>
<TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufio_available=20</TD>
<TD>bufio_fixed=0</TD>
<TD>bufio_used=0</TD>
<TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=10</TD>
<TD>bufmrce_fixed=0</TD>
<TD>bufmrce_used=0</TD>
<TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufr_available=20</TD>
<TD>bufr_fixed=0</TD>
<TD>bufr_used=0</TD>
<TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=5</TD>
<TD>mmcme2_adv_fixed=0</TD>
<TD>mmcme2_adv_used=0</TD>
<TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=5</TD>
<TD>plle2_adv_fixed=0</TD>
<TD>plle2_adv_used=0</TD>
<TD>plle2_adv_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'> <TD>dsp48e1_only_used=1</TD>
<TD>dsps_available=90</TD>
<TD>dsps_fixed=0</TD>
<TD>dsps_used=1</TD>
</TR><TR ALIGN='LEFT'> <TD>dsps_util_percentage=1.11</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
<TD>diff_hstl_i=0</TD>
<TD>diff_hstl_i_18=0</TD>
<TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
<TD>diff_hsul_12=0</TD>
<TD>diff_mobile_ddr=0</TD>
<TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
<TD>diff_sstl15=0</TD>
<TD>diff_sstl15_r=0</TD>
<TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
<TD>hstl_i=0</TD>
<TD>hstl_i_18=0</TD>
<TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
<TD>hsul_12=0</TD>
<TD>lvcmos12=0</TD>
<TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvcmos18=0</TD>
<TD>lvcmos25=0</TD>
<TD>lvcmos33=1</TD>
<TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
<TD>mini_lvds_25=0</TD>
<TD>mobile_ddr=0</TD>
<TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
<TD>rsds_25=0</TD>
<TD>sstl135=0</TD>
<TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
<TD>sstl15_r=0</TD>
<TD>sstl18_i=0</TD>
<TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'> <TD>block_ram_tile_available=50</TD>
<TD>block_ram_tile_fixed=0</TD>
<TD>block_ram_tile_used=0</TD>
<TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb18_available=100</TD>
<TD>ramb18_fixed=0</TD>
<TD>ramb18_used=0</TD>
<TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=50</TD>
<TD>ramb36_fifo_fixed=0</TD>
<TD>ramb36_fifo_used=0</TD>
<TD>ramb36_fifo_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
<TD>bufg_used=1</TD>
<TD>carry4_functional_category=CarryLogic</TD>
<TD>carry4_used=22</TD>
</TR><TR ALIGN='LEFT'> <TD>dsp48e1_functional_category=Block Arithmetic</TD>
<TD>dsp48e1_used=1</TD>
<TD>fdce_functional_category=Flop &amp; Latch</TD>
<TD>fdce_used=64</TD>
</TR><TR ALIGN='LEFT'> <TD>ibuf_functional_category=IO</TD>
<TD>ibuf_used=18</TD>
<TD>ldpe_functional_category=Flop &amp; Latch</TD>
<TD>ldpe_used=1</TD>
</TR><TR ALIGN='LEFT'> <TD>lut1_functional_category=LUT</TD>
<TD>lut1_used=3</TD>
<TD>lut2_functional_category=LUT</TD>
<TD>lut2_used=51</TD>
</TR><TR ALIGN='LEFT'> <TD>lut3_functional_category=LUT</TD>
<TD>lut3_used=16</TD>
<TD>lut4_functional_category=LUT</TD>
<TD>lut4_used=32</TD>
</TR><TR ALIGN='LEFT'> <TD>lut5_functional_category=LUT</TD>
<TD>lut5_used=4</TD>
<TD>lut6_functional_category=LUT</TD>
<TD>lut6_used=15</TD>
</TR><TR ALIGN='LEFT'> <TD>obuf_functional_category=IO</TD>
<TD>obuf_used=16</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'> <TD>f7_muxes_available=16300</TD>
<TD>f7_muxes_fixed=0</TD>
<TD>f7_muxes_used=0</TD>
<TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=8150</TD>
<TD>f8_muxes_fixed=0</TD>
<TD>f8_muxes_used=0</TD>
<TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
<TD>lut_as_logic_fixed=0</TD>
<TD>lut_as_logic_used=93</TD>
<TD>lut_as_logic_util_percentage=0.45</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
<TD>lut_as_memory_fixed=0</TD>
<TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=41600</TD>
<TD>register_as_flip_flop_fixed=0</TD>
<TD>register_as_flip_flop_used=64</TD>
<TD>register_as_flip_flop_util_percentage=0.15</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=41600</TD>
<TD>register_as_latch_fixed=0</TD>
<TD>register_as_latch_used=1</TD>
<TD>register_as_latch_util_percentage=&lt;0.01</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=20800</TD>
<TD>slice_luts_fixed=0</TD>
<TD>slice_luts_used=93</TD>
<TD>slice_luts_util_percentage=0.45</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=41600</TD>
<TD>slice_registers_fixed=0</TD>
<TD>slice_registers_used=65</TD>
<TD>slice_registers_util_percentage=0.16</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_distributed_ram_fixed=0</TD>
<TD>lut_as_distributed_ram_used=0</TD>
<TD>lut_as_logic_available=20800</TD>
<TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_used=93</TD>
<TD>lut_as_logic_util_percentage=0.45</TD>
<TD>lut_as_memory_available=9600</TD>
<TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
<TD>lut_as_shift_register_fixed=0</TD>
<TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
<TD>lut_in_front_of_the_register_is_unused_used=0</TD>
<TD>lut_in_front_of_the_register_is_used_fixed=0</TD>
<TD>lut_in_front_of_the_register_is_used_used=2</TD>
</TR><TR ALIGN='LEFT'> <TD>register_driven_from_outside_the_slice_fixed=2</TD>
<TD>register_driven_from_outside_the_slice_used=2</TD>
<TD>register_driven_from_within_the_slice_fixed=2</TD>
<TD>register_driven_from_within_the_slice_used=63</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_available=8150</TD>
<TD>slice_fixed=0</TD>
<TD>slice_registers_available=41600</TD>
<TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_registers_used=65</TD>
<TD>slice_registers_util_percentage=0.16</TD>
<TD>slice_used=31</TD>
<TD>slice_util_percentage=0.38</TD>
</TR><TR ALIGN='LEFT'> <TD>slicel_fixed=0</TD>
<TD>slicel_used=12</TD>
<TD>slicem_fixed=0</TD>
<TD>slicem_used=19</TD>
</TR><TR ALIGN='LEFT'> <TD>unique_control_sets_available=8150</TD>
<TD>unique_control_sets_fixed=8150</TD>
<TD>unique_control_sets_used=3</TD>
<TD>unique_control_sets_util_percentage=0.04</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_fixed=0.04</TD>
<TD>using_o5_and_o6_used=28</TD>
<TD>using_o5_output_only_fixed=28</TD>
<TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_fixed=0</TD>
<TD>using_o6_output_only_used=65</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
<TD>bscane2_fixed=0</TD>
<TD>bscane2_used=0</TD>
<TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
<TD>capturee2_fixed=0</TD>
<TD>capturee2_used=0</TD>
<TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
<TD>dna_port_fixed=0</TD>
<TD>dna_port_used=0</TD>
<TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
<TD>efuse_usr_fixed=0</TD>
<TD>efuse_usr_used=0</TD>
<TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
<TD>frame_ecce2_fixed=0</TD>
<TD>frame_ecce2_used=0</TD>
<TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
<TD>icape2_fixed=0</TD>
<TD>icape2_used=0</TD>
<TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>pcie_2_1_available=1</TD>
<TD>pcie_2_1_fixed=0</TD>
<TD>pcie_2_1_used=0</TD>
<TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
<TD>startupe2_fixed=0</TD>
<TD>startupe2_used=0</TD>
<TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
<TD>xadc_fixed=0</TD>
<TD>xadc_used=0</TD>
<TD>xadc_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
<TD>-bufg=default::12</TD>
<TD>-cascade_dsp=default::auto</TD>
<TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
<TD>-debug_log=default::[not_specified]</TD>
<TD>-directive=default::default</TD>
<TD>-fanout_limit=default::10000</TD>
</TR><TR ALIGN='LEFT'> <TD>-flatten_hierarchy=default::rebuilt</TD>
<TD>-fsm_extraction=default::auto</TD>
<TD>-gated_clock_conversion=default::off</TD>
<TD>-generic=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-include_dirs=default::[not_specified]</TD>
<TD>-keep_equivalent_registers=default::[not_specified]</TD>
<TD>-lint=default::[not_specified]</TD>
<TD>-max_bram=default::-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-max_bram_cascade_height=default::-1</TD>
<TD>-max_dsp=default::-1</TD>
<TD>-max_uram=default::-1</TD>
<TD>-max_uram_cascade_height=default::-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-mode=default::default</TD>
<TD>-name=default::[not_specified]</TD>
<TD>-no_lc=default::[not_specified]</TD>
<TD>-no_srlextract=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-no_timing_driven=default::[not_specified]</TD>
<TD>-os=default::[not_specified]</TD>
<TD>-part=xc7a35tcpg236-1</TD>
<TD>-resource_sharing=default::auto</TD>
</TR><TR ALIGN='LEFT'> <TD>-retiming=default::[not_specified]</TD>
<TD>-rtl=default::[not_specified]</TD>
<TD>-rtl_skip_constraints=default::[not_specified]</TD>
<TD>-rtl_skip_ip=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-seu_protect=default::none</TD>
<TD>-sfcu=default::[not_specified]</TD>
<TD>-shreg_min_size=default::3</TD>
<TD>-top=KittCar</TD>
</TR><TR ALIGN='LEFT'> <TD>-verilog_define=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>elapsed=00:00:21s</TD>
<TD>hls_ip=0</TD>
<TD>memory_gain=18.500MB</TD>
<TD>memory_peak=1018.504MB</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
</BODY>
</HTML>