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Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.

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PickleRick committed 2025-05-19 00:43:25 +02:00
1 parent 6ab3f7bcde
commit 5f30651763
7 files changed
+54 -98
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LAB3/design/diligent_jstk/diligent_jstk.bd
+18 -18
View File
@@ -591,30 +591,12 @@
}
},
"interface_nets": {
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
@@ -622,12 +604,30 @@
"system_ila_0/SLOT_1_AXIS"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS",
"system_ila_0/SLOT_0_AXIS"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
}
},
"nets": {
LAB3/design/diligent_jstk/diligent_jstk.bda
+7 -7
View File
@@ -25,18 +25,18 @@
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n0" target="n1">
<node id="n2">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n0" target="n2">
</edge>
<edge id="e1" source="n1" target="n2">
<edge id="e1" source="n2" target="n1">
</edge>
</graph>
</graphml>
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
+1 -1
View File
@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Sat May 17 14:20:44 2025
--Date : Sun May 18 23:39:32 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
LAB3/src/LFO.vhd
+1 -1
View File
@@ -149,7 +149,7 @@ BEGIN
signed(s_axis_tdata) * tri_counter
);
ELSE
lfo_product <= s_axis_tdata;
lfo_product <= s_axis_tdata & (TRIANGULAR_COUNTER_LENGHT - 1 downto 0 => '0');
END IF;
trigger <= '1';
LAB3/src/digilent_jstk2.vhd
+1 -1
View File
@@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
ENTITY digilent_jstk2 IS
GENERIC (
DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
DELAY_US : INTEGER := 300; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
);
LAB3/src/effect_selector.vhd
+1 -21
View File
@@ -1,24 +1,3 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/29/2024 10:12:03 AM
-- Design Name:
-- Module Name: effect_selector - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -38,6 +17,7 @@ entity effect_selector is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
effect : in STD_LOGIC;
jstck_x : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
jstck_y : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
LAB3/vivado/diligent_jstk/diligent_jstk.xpr
+25 -49
View File
@@ -95,17 +95,8 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_axi4stream_spi_master_0_0_1/diligent_jstk_axi4stream_spi_master_0_0.xci">
<Proxy FileSetName="diligent_jstk_axi4stream_spi_master_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_system_ila_0_0_1/diligent_jstk_system_ila_0_0.xci">
<Proxy FileSetName="diligent_jstk_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_jstk_uart_bridge_0_0_1/diligent_jstk_jstk_uart_bridge_0_0.xci">
<Proxy FileSetName="diligent_jstk_jstk_uart_bridge_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_digilent_jstk2_0_0_1/diligent_jstk_digilent_jstk2_0_0.xci">
<Proxy FileSetName="diligent_jstk_digilent_jstk2_0_0"/>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_proc_sys_reset_0_0_1/diligent_jstk_proc_sys_reset_0_0.xci">
<Proxy FileSetName="diligent_jstk_proc_sys_reset_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_AXI4Stream_UART_0_0_1/diligent_jstk_AXI4Stream_UART_0_0.xci">
<Proxy FileSetName="diligent_jstk_AXI4Stream_UART_0_0"/>
@@ -113,8 +104,17 @@
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_clk_wiz_0_0_1/diligent_jstk_clk_wiz_0_0.xci">
<Proxy FileSetName="diligent_jstk_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_proc_sys_reset_0_0_1/diligent_jstk_proc_sys_reset_0_0.xci">
<Proxy FileSetName="diligent_jstk_proc_sys_reset_0_0"/>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_jstk_uart_bridge_0_0_1/diligent_jstk_jstk_uart_bridge_0_0.xci">
<Proxy FileSetName="diligent_jstk_jstk_uart_bridge_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_axi4stream_spi_master_0_0_1/diligent_jstk_axi4stream_spi_master_0_0.xci">
<Proxy FileSetName="diligent_jstk_axi4stream_spi_master_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_system_ila_0_0_1/diligent_jstk_system_ila_0_0.xci">
<Proxy FileSetName="diligent_jstk_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_digilent_jstk2_0_0_1/diligent_jstk_digilent_jstk2_0_0.xci">
<Proxy FileSetName="diligent_jstk_digilent_jstk2_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PPRDIR/../../design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd">
@@ -238,9 +238,7 @@
</Run>
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_axi4stream_spi_master_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_axi4stream_spi_master_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -250,9 +248,7 @@
</Run>
<Run Id="diligent_jstk_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_system_ila_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -262,9 +258,7 @@
</Run>
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_jstk_uart_bridge_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -274,9 +268,7 @@
</Run>
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -286,9 +278,7 @@
</Run>
<Run Id="diligent_jstk_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_clk_wiz_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_clk_wiz_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -298,9 +288,7 @@
</Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -340,9 +328,7 @@
</Run>
<Run Id="diligent_jstk_axi4stream_spi_master_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_axi4stream_spi_master_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_axi4stream_spi_master_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_axi4stream_spi_master_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -359,9 +345,7 @@
</Run>
<Run Id="diligent_jstk_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_system_ila_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_system_ila_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -378,9 +362,7 @@
</Run>
<Run Id="diligent_jstk_jstk_uart_bridge_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -397,9 +379,7 @@
</Run>
<Run Id="diligent_jstk_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -416,9 +396,7 @@
</Run>
<Run Id="diligent_jstk_clk_wiz_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_clk_wiz_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -435,9 +413,7 @@
</Run>
<Run Id="diligent_jstk_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>