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Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.

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This commit is contained in:
Davide Cavagnola
2025-05-19 00:43:25 +02:00
parent 6ab3f7bcde
commit 5f30651763
7 changed files with 54 additions and 98 deletions
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14
LAB3/design/diligent_jstk/diligent_jstk.bda
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@@ -25,18 +25,18 @@
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n0" target="n1">
<node id="n2">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n0" target="n2">
</edge>
<edge id="e1" source="n1" target="n2">
<edge id="e1" source="n2" target="n1">
</edge>
</graph>
</graphml>