Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.

LAB3/src/LFO.vhd

@@ -149,7 +149,7 @@ BEGIN
                             signed(s_axis_tdata) * tri_counter
                             );
                     ELSE
-                        lfo_product <= s_axis_tdata;
+                        lfo_product <= s_axis_tdata & (TRIANGULAR_COUNTER_LENGHT - 1 downto 0 => '0');
                     END IF;
 
                     trigger <= '1';

LAB3/src/digilent_jstk2.vhd

@@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY digilent_jstk2 IS
 	GENERIC (
-		DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
+		DELAY_US : INTEGER := 300; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
 		CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
 		SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
 	);

LAB3/src/effect_selector.vhd

@@ -1,24 +1,3 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date: 04/29/2024 10:12:03 AM
--- Design Name: 
--- Module Name: effect_selector - Behavioral
--- Project Name: 
--- Target Devices: 
--- Tool Versions: 
--- Description: 
--- 
--- Dependencies: 
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- 
-----------------------------------------------------------------------------------
-
-
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
@@ -38,6 +17,7 @@ entity effect_selector is
     Port (
         aclk : in STD_LOGIC;
         aresetn : in STD_LOGIC;
+        
         effect : in STD_LOGIC;
         jstck_x : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);
         jstck_y : in STD_LOGIC_VECTOR(JOYSTICK_LENGHT-1 downto 0);