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Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.

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This commit is contained in:
Davide Cavagnola
2025-05-19 00:43:25 +02:00
parent 6ab3f7bcde
commit 5f30651763
7 changed files with 54 additions and 98 deletions
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LAB3/src/digilent_jstk2.vhd
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@@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
ENTITY digilent_jstk2 IS
GENERIC (
DELAY_US : INTEGER := 100; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
DELAY_US : INTEGER := 300; -- Delay (in us) between two packets - Required by the SPI IP-Core tested with 25us doesn't work
CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
);