Add initial design files and project configuration for LAB3
- Created a new Block Design Archive (lab_3.bda) for LAB3, defining nodes and edges for the design. - Added a placeholder README file in the simulation directory. - Initialized a Vivado project file (lab3.xpr) with configuration settings and source files for synthesis and simulation. - Updated vhdl_ls.toml to include LAB3 source and simulation files for VHDL language server support.
This commit is contained in:
1
.gitignore
vendored
1
.gitignore
vendored
@@ -42,7 +42,6 @@
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*.qws
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*.wdf
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*.lpr
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*.xdc
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*.bxml
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13
LAB3/cons/io.xdc
Normal file
13
LAB3/cons/io.xdc
Normal file
@@ -0,0 +1,13 @@
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# SPI connected to JA, top row
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set_property PACKAGE_PIN J1 [get_ports SPI_M_0_ss_io]
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set_property PACKAGE_PIN G2 [get_ports SPI_M_0_sck_io]
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set_property PACKAGE_PIN L2 [get_ports SPI_M_0_io0_io]
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set_property PACKAGE_PIN J2 [get_ports SPI_M_0_io1_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io0_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_io1_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_sck_io]
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set_property IOSTANDARD LVCMOS33 [get_ports SPI_M_0_ss_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io0_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_io1_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_sck_io]
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set_property OFFCHIP_TERM NONE [get_ports SPI_M_0_ss_io]
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2104
LAB3/design/lab_3/lab_3.bd
Normal file
2104
LAB3/design/lab_3/lab_3.bd
Normal file
File diff suppressed because it is too large
Load Diff
42
LAB3/design/lab_3/lab_3.bda
Normal file
42
LAB3/design/lab_3/lab_3.bda
Normal file
@@ -0,0 +1,42 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
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<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
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<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
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<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
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<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
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<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
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<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
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<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
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<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
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<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
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<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
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<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
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<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
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<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
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<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
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<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
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<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
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<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
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<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
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<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
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<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
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<node id="n0">
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<data key="VH">2</data>
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<data key="VM">lab_3</data>
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<data key="VT">VR</data>
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</node>
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<node id="n1">
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<data key="VM">lab_3</data>
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<data key="VT">BC</data>
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</node>
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<node id="n2">
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<data key="TU">active</data>
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<data key="VH">2</data>
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<data key="VT">PM</data>
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</node>
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<edge id="e0" source="n1" target="n0">
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</edge>
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<edge id="e1" source="n0" target="n2">
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</edge>
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</graph>
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</graphml>
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3
LAB3/sim/ReadMe.md
Normal file
3
LAB3/sim/ReadMe.md
Normal file
@@ -0,0 +1,3 @@
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# Placeholder
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This is a placeholder.
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327
LAB3/vivado/lab3/lab3.xpr
Normal file
327
LAB3/vivado/lab3/lab3.xpr
Normal file
@@ -0,0 +1,327 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2020.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="54" Path="C:/DESD/LAB3/vivado/lab3/lab3.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="45a33585426e4c4e913883d4be838656"/>
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<Option Name="Part" Val="xc7a35tcpg236-1"/>
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||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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||||
<Option Name="CompiledLibDirXSim" Val=""/>
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||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirIES" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirIES" Val=""/>
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||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="TargetLanguage" Val="VHDL"/>
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<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
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<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../ip"/>
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||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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||||
<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||
<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSABoardId" Val="basys3"/>
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||||
<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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||||
<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||
<Option Name="WTXSimExportSim" Val="1"/>
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<Option Name="WTModelSimExportSim" Val="1"/>
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<Option Name="WTQuestaExportSim" Val="1"/>
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||||
<Option Name="WTIesExportSim" Val="1"/>
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||||
<Option Name="WTVcsExportSim" Val="1"/>
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||||
<Option Name="WTRivieraExportSim" Val="1"/>
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<Option Name="WTActivehdlExportSim" Val="1"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../../src/LFO.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../src/balance_controller.vhd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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||||
</File>
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||||
<File Path="$PPRDIR/../../src/debouncer.vhd">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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||||
</File>
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<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
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||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/edge_detector_toggle.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/effect_selector.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/jstk_uart_bridge.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/led_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/led_level_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/moving_average_filter.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/moving_average_filter_en.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/mute_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/volume_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/volume_multiplier.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/volume_saturator.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../design/lab_3/lab_3.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LFO"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopArchitecture" Val="Behavioral"/>
|
||||
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/LFO.vhd"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../cons/io.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LFO"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopArchitecture" Val="Behavioral"/>
|
||||
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/LFO.vhd"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
@@ -15,10 +15,10 @@ lab2_lib.files = [
|
||||
"LAB2/sim/**/*.vhd"
|
||||
]
|
||||
|
||||
# lab3_lib.files = [
|
||||
# "LAB3/src/**/*.vhd",
|
||||
# "LAB3/sim/**/*.vhd"
|
||||
# ]
|
||||
lab3_lib.files = [
|
||||
"LAB3/src/**/*.vhd",
|
||||
"LAB3/sim/**/*.vhd"
|
||||
]
|
||||
|
||||
xpm.files = [
|
||||
"C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd"
|
||||
|
||||
Reference in New Issue
Block a user