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Enhance bram_writer and testbench: add data handling for convolution, update state machine, and introduce new configuration files for simulation

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This commit is contained in:
Davide Cavagnola
2025-04-17 21:29:02 +02:00
parent 7ee12b37fe
commit 667632bfa3
4 changed files with 358 additions and 15 deletions
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6
LAB2/sim/tb_bram_writer.vhd
View File

@@ -127,6 +127,12 @@ BEGIN
wait until write_ok = '1';
wait until rising_edge(clk);
-- Require data
for i in 0 to IMG_SIZE*IMG_SIZE-1 loop
conv_addr <= std_logic_vector(to_unsigned(i, ADDR_WIDTH));
wait until rising_edge(clk);
end loop;
-- Simulate convolution done
done_conv <= '1';
wait until rising_edge(clk);

40
LAB2/src/bram_writer.vhd
View File

@@ -46,11 +46,13 @@ ARCHITECTURE rtl OF bram_writer IS
);
END COMPONENT;
TYPE state_type IS (IDLE, RECEIVING, CONVOLUTION);
TYPE state_type IS (IDLE, RECEIVING, CHECK_START_CONV, CONVOLUTION);
SIGNAL state : state_type := IDLE;
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL bram_data_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- BRAM data output
SIGNAL bram_data_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- BRAM data input
SIGNAL bram_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- BRAM address
SIGNAL bram_we : STD_LOGIC := '0'; -- Write enable signal for BRAM
@@ -67,14 +69,17 @@ BEGIN
clk => clk,
aresetn => aresetn,
addr => bram_addr,
dout => conv_data,
din => s_axis_tdata,
dout => bram_data_out,
din => bram_data_in,
we => bram_we
);
-- Assign AXIS ready signal
s_axis_tready <= s_axis_tready_int;
-- Binding BRAM data to output
conv_data <= bram_data_out(6 DOWNTO 0);
-- Select BRAM address based on state
WITH state SELECT bram_addr <= conv_addr WHEN CONVOLUTION,
wr_addr WHEN OTHERS;
@@ -112,6 +117,7 @@ BEGIN
-- valid data received, start receiving
wr_addr <= (OTHERS => '0');
bram_we <= '1'; -- Enable write to BRAM
bram_data_in <= s_axis_tdata; -- Write data to BRAM
state <= RECEIVING;
END IF;
@@ -126,25 +132,29 @@ BEGIN
-- Increment write address and write data to BRAM
wr_addr <= STD_LOGIC_VECTOR(unsigned(wr_addr) + 1);
bram_we <= '1'; -- Enable write to BRAM
bram_data_in <= s_axis_tdata; -- Write data to BRAM
-- Check for last data signal
IF s_axis_tlast = '1' THEN
-- Check for underflow: if not enough data received
IF unsigned(wr_addr) < (IMG_SIZE ** 2 - 2) THEN
underflow <= '1';
state <= IDLE;
ELSE
-- Data reception complete, start convolution
write_ok <= '1';
s_axis_tready_int <= '0';
start_conv <= '1';
state <= CONVOLUTION;
END IF;
state <= CHECK_START_CONV;
END IF;
END IF;
END IF;
WHEN CHECK_START_CONV =>
-- Check for underflow: if not enough data received
IF unsigned(wr_addr) < (IMG_SIZE ** 2 - 2) THEN
underflow <= '1';
state <= IDLE;
ELSE
-- Data reception complete, start convolution
write_ok <= '1';
s_axis_tready_int <= '0';
start_conv <= '1';
state <= CONVOLUTION;
END IF;
WHEN CONVOLUTION =>
-- Wait for convolution to finish
s_axis_tready_int <= '0';

220
LAB2/vivado/bram_writer_test/bram_writer_test.xpr Normal file
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@@ -0,0 +1,220 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/bram_writer_test/bram_writer_test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="db44c0b9410c4eb8a804a71d784cd439"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="22"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/bram_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_writer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="bram_writer"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<File Path="$PPRDIR/../../sim/tb_bram_writer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_bram_writer_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_bram_writer"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_bram_writer_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

107
LAB2/vivado/bram_writer_test/tb_bram_writer_behav.wcfg Normal file
View File

@@ -0,0 +1,107 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_bram_writer_behav.wdb" id="1">
<top_modules>
<top_module name="tb_bram_writer" />
<top_module name="vcomponents" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="274601fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="340"></NameColumnWidth>
<ValueColumnWidth column_width="155"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="21" />
<wvobject fp_name="/tb_bram_writer/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/aresetn" type="logic">
<obj_property name="ElementShortName">aresetn</obj_property>
<obj_property name="ObjectShortName">aresetn</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider36">
<obj_property name="label">AXI4</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tdata" type="array">
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tvalid" type="logic">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tready" type="logic">
<obj_property name="ElementShortName">s_axis_tready</obj_property>
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tlast" type="logic">
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider37">
<obj_property name="label">FSM</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/state" type="other">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider38">
<obj_property name="label">BRAM</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/bram_addr" type="array">
<obj_property name="ElementShortName">bram_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">bram_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/wr_addr" type="array">
<obj_property name="ElementShortName">wr_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">wr_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/bram_we" type="logic">
<obj_property name="ElementShortName">bram_we</obj_property>
<obj_property name="ObjectShortName">bram_we</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/conv_addr" type="array">
<obj_property name="ElementShortName">conv_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">conv_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/conv_data" type="array">
<obj_property name="ElementShortName">conv_data[6:0]</obj_property>
<obj_property name="ObjectShortName">conv_data[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/start_conv" type="logic">
<obj_property name="ElementShortName">start_conv</obj_property>
<obj_property name="ObjectShortName">start_conv</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/done_conv" type="logic">
<obj_property name="ElementShortName">done_conv</obj_property>
<obj_property name="ObjectShortName">done_conv</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider39">
<obj_property name="label">Out status</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/write_ok" type="logic">
<obj_property name="ElementShortName">write_ok</obj_property>
<obj_property name="ObjectShortName">write_ok</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/overflow" type="logic">
<obj_property name="ElementShortName">overflow</obj_property>
<obj_property name="ObjectShortName">overflow</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/underflow" type="logic">
<obj_property name="ElementShortName">underflow</obj_property>
<obj_property name="ObjectShortName">underflow</obj_property>
</wvobject>
</wave_config>