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Add moving average filter testbench and configuration files; refactor signal handling in filter components

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This commit is contained in:
Davide Cavagnola
2025-05-23 12:49:46 +02:00
parent d3dd458825
commit 6cb0e4095e
5 changed files with 650 additions and 23 deletions
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17
LAB3/src/all_pass_filter.vhd
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@@ -24,7 +24,6 @@ END all_pass_filter;
ARCHITECTURE Behavioral OF all_pass_filter IS
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
@@ -33,17 +32,17 @@ BEGIN
-- of the moving_average_filter, but does not process or modify the samples.
-- It simply passes input data to the output unchanged, ensuring the same latency and interface behavior.
-- Output assignments
s_axis_tready <= s_axis_tready_int;
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
PROCESS (aclk)
BEGIN
IF rising_edge(aclk) THEN
IF aresetn = '0' THEN
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
ELSE
-- Clear valid flag when master interface is ready
@@ -51,16 +50,12 @@ BEGIN
m_axis_tvalid_int <= '0';
END IF;
-- Hndle data transfer
IF s_axis_tvalid = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
s_axis_tready_int <= '1';
-- Handle data transfer
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= s_axis_tdata;
m_axis_tlast <= s_axis_tlast;
ELSE
s_axis_tready_int <= '0';
END IF;
END IF;

22
LAB3/src/moving_average_filter.vhd
View File

@@ -41,14 +41,13 @@ ARCHITECTURE Behavioral OF moving_average_filter IS
SIGNAL sum_sx : signed(TDATA_WIDTH + FILTER_ORDER_POWER - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_ptr_sx : INTEGER RANGE 0 TO FILTER_ORDER - 1 := 0;
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
BEGIN
-- Output assignments
-- Assigning the output signals
m_axis_tvalid <= m_axis_tvalid_int;
s_axis_tready <= s_axis_tready_int;
s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
PROCESS (aclk)
BEGIN
@@ -57,14 +56,14 @@ BEGIN
IF aresetn = '0' THEN
samples_dx <= (OTHERS => (OTHERS => '0'));
samples_sx <= (OTHERS => (OTHERS => '0'));
sum_dx <= (OTHERS => '0');
sum_sx <= (OTHERS => '0');
wr_ptr_dx <= 0;
wr_ptr_sx <= 0;
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
m_axis_tdata <= (OTHERS => '0');
ELSE
-- Clear valid flag when master interface is ready
@@ -73,8 +72,10 @@ BEGIN
END IF;
-- Get and process data
IF s_axis_tvalid = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
IF s_axis_tlast = '1' THEN
IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
IF s_axis_tlast = '1' THEN
-- Right channel
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
samples_dx(wr_ptr_dx) <= signed(s_axis_tdata);
@@ -95,6 +96,7 @@ BEGIN
)
);
ELSE
-- Left channel
-- Circular buffer overwrite oldest saple with the new one from next clk cycle
samples_sx(wr_ptr_sx) <= signed(s_axis_tdata);
@@ -116,13 +118,9 @@ BEGIN
);
END IF;
s_axis_tready_int <= '1';
m_axis_tvalid_int <= '1';
m_axis_tlast <= s_axis_tlast;
ELSE
s_axis_tready_int <= '0';
END IF;
END IF;