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LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd

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+--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------
+--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
+--Date        : Tue Apr 22 22:40:46 2025
+--Host        : Davide-Samsung running 64-bit major release  (build 9200)
+--Command     : generate_target pak_depak_wrapper.bd
+--Design      : pak_depak_wrapper
+--Purpose     : IP block netlist
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity pak_depak_wrapper is
+  port (
+    reset : in STD_LOGIC;
+    sys_clock : in STD_LOGIC;
+    usb_uart_rxd : in STD_LOGIC;
+    usb_uart_txd : out STD_LOGIC
+  );
+end pak_depak_wrapper;
+
+architecture STRUCTURE of pak_depak_wrapper is
+  component pak_depak is
+  port (
+    reset : in STD_LOGIC;
+    sys_clock : in STD_LOGIC;
+    usb_uart_txd : out STD_LOGIC;
+    usb_uart_rxd : in STD_LOGIC
+  );
+  end component pak_depak;
+begin
+pak_depak_i: component pak_depak
+     port map (
+      reset => reset,
+      sys_clock => sys_clock,
+      usb_uart_rxd => usb_uart_rxd,
+      usb_uart_txd => usb_uart_txd
+    );
+end STRUCTURE;