Create design folder and update projects
This commit is contained in:
8
.gitignore
vendored
8
.gitignore
vendored
@@ -69,3 +69,11 @@ vivado*.backup.log
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# SDK workspace
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# SDK workspace
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.sdk/
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.sdk/
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# design files
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**/design/**/ipshared/
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**/design/**/ip/
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**/design/**/sim/
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**/design/**/synth/
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**/design/**/ui/
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**/design/**/hw_handoff/
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49
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
Normal file
49
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
Normal file
@@ -0,0 +1,49 @@
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Tue Apr 22 22:53:03 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target lab_2_wrapper.bd
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--Design : lab_2_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity lab_2_wrapper is
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port (
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led_of : out STD_LOGIC;
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led_ok : out STD_LOGIC;
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led_uf : out STD_LOGIC;
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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);
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end lab_2_wrapper;
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architecture STRUCTURE of lab_2_wrapper is
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component lab_2 is
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port (
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led_of : out STD_LOGIC;
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led_ok : out STD_LOGIC;
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led_uf : out STD_LOGIC;
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sys_clock : in STD_LOGIC;
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reset : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component lab_2;
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begin
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lab_2_i: component lab_2
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port map (
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led_of => led_of,
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led_ok => led_ok,
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led_uf => led_uf,
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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1338
LAB2/design/lab_2/lab_2.bd
Normal file
1338
LAB2/design/lab_2/lab_2.bd
Normal file
File diff suppressed because it is too large
Load Diff
42
LAB2/design/lab_2/lab_2.bda
Normal file
42
LAB2/design/lab_2/lab_2.bda
Normal file
@@ -0,0 +1,42 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
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<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
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<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
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<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
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<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
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<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
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<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
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<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
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<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
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<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
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<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
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<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
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<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
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<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
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<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
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<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
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<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
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<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
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<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
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<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
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<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
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<node id="n0">
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<data key="VH">2</data>
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<data key="VM">lab_2</data>
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<data key="VT">VR</data>
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</node>
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<node id="n1">
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<data key="TU">active</data>
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<data key="VH">2</data>
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<data key="VT">PM</data>
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</node>
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<node id="n2">
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<data key="VM">lab_2</data>
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<data key="VT">BC</data>
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</node>
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<edge id="e0" source="n2" target="n0">
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</edge>
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<edge id="e1" source="n0" target="n1">
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</edge>
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</graph>
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</graphml>
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40
LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd
Normal file
40
LAB2/design/pak_depak/hdl/pak_depak_wrapper.vhd
Normal file
@@ -0,0 +1,40 @@
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Tue Apr 22 22:40:46 2025
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|
--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target pak_depak_wrapper.bd
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--Design : pak_depak_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity pak_depak_wrapper is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC
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|
);
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end pak_depak_wrapper;
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architecture STRUCTURE of pak_depak_wrapper is
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component pak_depak is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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usb_uart_txd : out STD_LOGIC;
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usb_uart_rxd : in STD_LOGIC
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);
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end component pak_depak;
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begin
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pak_depak_i: component pak_depak
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port map (
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reset => reset,
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sys_clock => sys_clock,
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usb_uart_rxd => usb_uart_rxd,
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usb_uart_txd => usb_uart_txd
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);
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end STRUCTURE;
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559
LAB2/design/pak_depak/pak_depak.bd
Normal file
559
LAB2/design/pak_depak/pak_depak.bd
Normal file
@@ -0,0 +1,559 @@
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{
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"design": {
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"design_info": {
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"boundary_crc": "0x9157799052A71E23",
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|
"device": "xc7a35tcpg236-1",
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|
"name": "pak_depak",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "None",
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"tool_version": "2020.2",
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|
"validated": "true"
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|
},
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|
"design_tree": {
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|
"proc_sys_reset_0": "",
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|
"clk_wiz_0": "",
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"AXI4Stream_UART_0": "",
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|
"packetizer_0": "",
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|
"depacketizer_0": ""
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||||||
|
},
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|
"interface_ports": {
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||||||
|
"usb_uart": {
|
||||||
|
"mode": "Master",
|
||||||
|
"vlnv": "xilinx.com:interface:uart_rtl:1.0"
|
||||||
|
}
|
||||||
|
},
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||||||
|
"ports": {
|
||||||
|
"reset": {
|
||||||
|
"type": "rst",
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|
"direction": "I",
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|
"parameters": {
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||||||
|
"INSERT_VIP": {
|
||||||
|
"value": "0",
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||||||
|
"value_src": "default"
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||||||
|
},
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||||||
|
"POLARITY": {
|
||||||
|
"value": "ACTIVE_HIGH"
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||||||
|
}
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||||||
|
}
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||||||
|
},
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||||||
|
"sys_clock": {
|
||||||
|
"type": "clk",
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||||||
|
"direction": "I",
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||||||
|
"parameters": {
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "pak_depak_sys_clock",
|
||||||
|
"value_src": "default"
|
||||||
|
},
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||||||
|
"FREQ_HZ": {
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||||||
|
"value": "100000000"
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||||||
|
},
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||||||
|
"FREQ_TOLERANCE_HZ": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "default"
|
||||||
|
},
|
||||||
|
"INSERT_VIP": {
|
||||||
|
"value": "0",
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||||||
|
"value_src": "default"
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||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.000"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"components": {
|
||||||
|
"proc_sys_reset_0": {
|
||||||
|
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||||
|
"xci_name": "pak_depak_proc_sys_reset_0_0",
|
||||||
|
"xci_path": "ip\\pak_depak_proc_sys_reset_0_0\\pak_depak_proc_sys_reset_0_0.xci",
|
||||||
|
"inst_hier_path": "proc_sys_reset_0",
|
||||||
|
"parameters": {
|
||||||
|
"RESET_BOARD_INTERFACE": {
|
||||||
|
"value": "reset"
|
||||||
|
},
|
||||||
|
"USE_BOARD_FLOW": {
|
||||||
|
"value": "true"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"clk_wiz_0": {
|
||||||
|
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
|
||||||
|
"xci_name": "pak_depak_clk_wiz_0_1",
|
||||||
|
"xci_path": "ip\\pak_depak_clk_wiz_0_1\\pak_depak_clk_wiz_0_1.xci",
|
||||||
|
"inst_hier_path": "clk_wiz_0",
|
||||||
|
"parameters": {
|
||||||
|
"CLK_IN1_BOARD_INTERFACE": {
|
||||||
|
"value": "sys_clock"
|
||||||
|
},
|
||||||
|
"RESET_BOARD_INTERFACE": {
|
||||||
|
"value": "reset"
|
||||||
|
},
|
||||||
|
"USE_BOARD_FLOW": {
|
||||||
|
"value": "true"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"AXI4Stream_UART_0": {
|
||||||
|
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
|
||||||
|
"xci_name": "pak_depak_AXI4Stream_UART_0_0",
|
||||||
|
"xci_path": "ip\\pak_depak_AXI4Stream_UART_0_0\\pak_depak_AXI4Stream_UART_0_0.xci",
|
||||||
|
"inst_hier_path": "AXI4Stream_UART_0",
|
||||||
|
"parameters": {
|
||||||
|
"UART_BOARD_INTERFACE": {
|
||||||
|
"value": "usb_uart"
|
||||||
|
},
|
||||||
|
"USE_BOARD_FLOW": {
|
||||||
|
"value": "true"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"packetizer_0": {
|
||||||
|
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
|
||||||
|
"xci_name": "pak_depak_packetizer_0_0",
|
||||||
|
"xci_path": "ip\\pak_depak_packetizer_0_0\\pak_depak_packetizer_0_0.xci",
|
||||||
|
"inst_hier_path": "packetizer_0",
|
||||||
|
"reference_info": {
|
||||||
|
"ref_type": "hdl",
|
||||||
|
"ref_name": "packetizer",
|
||||||
|
"boundary_crc": "0x0"
|
||||||
|
},
|
||||||
|
"interface_ports": {
|
||||||
|
"m_axis": {
|
||||||
|
"mode": "Master",
|
||||||
|
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TDEST_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TID_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TUSER_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TREADY": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TSTRB": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TKEEP": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TLAST": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"FREQ_HZ": {
|
||||||
|
"value": "100000000",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.0",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "/clk_wiz_0_clk_out1",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": {
|
||||||
|
"physical_name": "m_axis_tdata",
|
||||||
|
"direction": "O",
|
||||||
|
"left": "7",
|
||||||
|
"right": "0"
|
||||||
|
},
|
||||||
|
"TVALID": {
|
||||||
|
"physical_name": "m_axis_tvalid",
|
||||||
|
"direction": "O"
|
||||||
|
},
|
||||||
|
"TREADY": {
|
||||||
|
"physical_name": "m_axis_tready",
|
||||||
|
"direction": "I"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"s_axis": {
|
||||||
|
"mode": "Slave",
|
||||||
|
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TDEST_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TID_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TUSER_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TREADY": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TSTRB": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TKEEP": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TLAST": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"FREQ_HZ": {
|
||||||
|
"value": "100000000",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.0",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "/clk_wiz_0_clk_out1",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": {
|
||||||
|
"physical_name": "s_axis_tdata",
|
||||||
|
"direction": "I",
|
||||||
|
"left": "7",
|
||||||
|
"right": "0"
|
||||||
|
},
|
||||||
|
"TLAST": {
|
||||||
|
"physical_name": "s_axis_tlast",
|
||||||
|
"direction": "I"
|
||||||
|
},
|
||||||
|
"TVALID": {
|
||||||
|
"physical_name": "s_axis_tvalid",
|
||||||
|
"direction": "I"
|
||||||
|
},
|
||||||
|
"TREADY": {
|
||||||
|
"physical_name": "s_axis_tready",
|
||||||
|
"direction": "O"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"ports": {
|
||||||
|
"clk": {
|
||||||
|
"type": "clk",
|
||||||
|
"direction": "I",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": {
|
||||||
|
"value": "m_axis:s_axis",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"ASSOCIATED_RESET": {
|
||||||
|
"value": "aresetn",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"FREQ_HZ": {
|
||||||
|
"value": "100000000",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.0",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "/clk_wiz_0_clk_out1",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn": {
|
||||||
|
"type": "rst",
|
||||||
|
"direction": "I",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": {
|
||||||
|
"value": "ACTIVE_LOW",
|
||||||
|
"value_src": "constant"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"depacketizer_0": {
|
||||||
|
"vlnv": "xilinx.com:module_ref:depacketizer:1.0",
|
||||||
|
"xci_name": "pak_depak_depacketizer_0_0",
|
||||||
|
"xci_path": "ip\\pak_depak_depacketizer_0_0\\pak_depak_depacketizer_0_0.xci",
|
||||||
|
"inst_hier_path": "depacketizer_0",
|
||||||
|
"reference_info": {
|
||||||
|
"ref_type": "hdl",
|
||||||
|
"ref_name": "depacketizer",
|
||||||
|
"boundary_crc": "0x0"
|
||||||
|
},
|
||||||
|
"interface_ports": {
|
||||||
|
"m_axis": {
|
||||||
|
"mode": "Master",
|
||||||
|
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TDEST_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TID_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TUSER_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TREADY": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TSTRB": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TKEEP": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TLAST": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"FREQ_HZ": {
|
||||||
|
"value": "100000000",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.0",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "/clk_wiz_0_clk_out1",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": {
|
||||||
|
"physical_name": "m_axis_tdata",
|
||||||
|
"direction": "O",
|
||||||
|
"left": "7",
|
||||||
|
"right": "0"
|
||||||
|
},
|
||||||
|
"TLAST": {
|
||||||
|
"physical_name": "m_axis_tlast",
|
||||||
|
"direction": "O"
|
||||||
|
},
|
||||||
|
"TVALID": {
|
||||||
|
"physical_name": "m_axis_tvalid",
|
||||||
|
"direction": "O"
|
||||||
|
},
|
||||||
|
"TREADY": {
|
||||||
|
"physical_name": "m_axis_tready",
|
||||||
|
"direction": "I"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"s_axis": {
|
||||||
|
"mode": "Slave",
|
||||||
|
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
|
||||||
|
"parameters": {
|
||||||
|
"TDATA_NUM_BYTES": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TDEST_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TID_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"TUSER_WIDTH": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TREADY": {
|
||||||
|
"value": "1",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TSTRB": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TKEEP": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"HAS_TLAST": {
|
||||||
|
"value": "0",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"FREQ_HZ": {
|
||||||
|
"value": "100000000",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.0",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "/clk_wiz_0_clk_out1",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"TDATA": {
|
||||||
|
"physical_name": "s_axis_tdata",
|
||||||
|
"direction": "I",
|
||||||
|
"left": "7",
|
||||||
|
"right": "0"
|
||||||
|
},
|
||||||
|
"TVALID": {
|
||||||
|
"physical_name": "s_axis_tvalid",
|
||||||
|
"direction": "I"
|
||||||
|
},
|
||||||
|
"TREADY": {
|
||||||
|
"physical_name": "s_axis_tready",
|
||||||
|
"direction": "O"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"ports": {
|
||||||
|
"clk": {
|
||||||
|
"type": "clk",
|
||||||
|
"direction": "I",
|
||||||
|
"parameters": {
|
||||||
|
"ASSOCIATED_BUSIF": {
|
||||||
|
"value": "m_axis:s_axis",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"ASSOCIATED_RESET": {
|
||||||
|
"value": "aresetn",
|
||||||
|
"value_src": "constant"
|
||||||
|
},
|
||||||
|
"FREQ_HZ": {
|
||||||
|
"value": "100000000",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"PHASE": {
|
||||||
|
"value": "0.0",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
},
|
||||||
|
"CLK_DOMAIN": {
|
||||||
|
"value": "/clk_wiz_0_clk_out1",
|
||||||
|
"value_src": "ip_prop"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"aresetn": {
|
||||||
|
"type": "rst",
|
||||||
|
"direction": "I",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": {
|
||||||
|
"value": "ACTIVE_LOW",
|
||||||
|
"value_src": "constant"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"interface_nets": {
|
||||||
|
"AXI4Stream_UART_0_UART": {
|
||||||
|
"interface_ports": [
|
||||||
|
"usb_uart",
|
||||||
|
"AXI4Stream_UART_0/UART"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"depacketizer_0_m_axis": {
|
||||||
|
"interface_ports": [
|
||||||
|
"depacketizer_0/m_axis",
|
||||||
|
"packetizer_0/s_axis"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"AXI4Stream_UART_0_M00_AXIS_RX": {
|
||||||
|
"interface_ports": [
|
||||||
|
"AXI4Stream_UART_0/M00_AXIS_RX",
|
||||||
|
"depacketizer_0/s_axis"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"packetizer_0_m_axis": {
|
||||||
|
"interface_ports": [
|
||||||
|
"packetizer_0/m_axis",
|
||||||
|
"AXI4Stream_UART_0/S00_AXIS_TX"
|
||||||
|
]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"nets": {
|
||||||
|
"reset_1": {
|
||||||
|
"ports": [
|
||||||
|
"reset",
|
||||||
|
"proc_sys_reset_0/ext_reset_in",
|
||||||
|
"clk_wiz_0/reset"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"sys_clock_1": {
|
||||||
|
"ports": [
|
||||||
|
"sys_clock",
|
||||||
|
"clk_wiz_0/clk_in1"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"clk_wiz_0_clk_out1": {
|
||||||
|
"ports": [
|
||||||
|
"clk_wiz_0/clk_out1",
|
||||||
|
"AXI4Stream_UART_0/clk_uart",
|
||||||
|
"proc_sys_reset_0/slowest_sync_clk",
|
||||||
|
"AXI4Stream_UART_0/m00_axis_rx_aclk",
|
||||||
|
"AXI4Stream_UART_0/s00_axis_tx_aclk",
|
||||||
|
"packetizer_0/clk",
|
||||||
|
"depacketizer_0/clk"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"proc_sys_reset_0_peripheral_reset": {
|
||||||
|
"ports": [
|
||||||
|
"proc_sys_reset_0/peripheral_reset",
|
||||||
|
"AXI4Stream_UART_0/rst"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"clk_wiz_0_locked": {
|
||||||
|
"ports": [
|
||||||
|
"clk_wiz_0/locked",
|
||||||
|
"proc_sys_reset_0/dcm_locked"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"proc_sys_reset_0_peripheral_aresetn": {
|
||||||
|
"ports": [
|
||||||
|
"proc_sys_reset_0/peripheral_aresetn",
|
||||||
|
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
|
||||||
|
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
|
||||||
|
"packetizer_0/aresetn",
|
||||||
|
"depacketizer_0/aresetn"
|
||||||
|
]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
42
LAB2/design/pak_depak/pak_depak.bda
Normal file
42
LAB2/design/pak_depak/pak_depak.bda
Normal file
@@ -0,0 +1,42 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
|
||||||
|
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
|
||||||
|
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
|
||||||
|
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
|
||||||
|
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
|
||||||
|
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
|
||||||
|
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
|
||||||
|
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
|
||||||
|
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
|
||||||
|
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
|
||||||
|
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
|
||||||
|
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
|
||||||
|
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
|
||||||
|
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
|
||||||
|
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
|
||||||
|
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
|
||||||
|
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
|
||||||
|
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
|
||||||
|
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
|
||||||
|
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
|
||||||
|
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
|
||||||
|
<node id="n0">
|
||||||
|
<data key="VM">pak_depak</data>
|
||||||
|
<data key="VT">BC</data>
|
||||||
|
</node>
|
||||||
|
<node id="n1">
|
||||||
|
<data key="VH">2</data>
|
||||||
|
<data key="VM">pak_depak</data>
|
||||||
|
<data key="VT">VR</data>
|
||||||
|
</node>
|
||||||
|
<node id="n2">
|
||||||
|
<data key="TU">active</data>
|
||||||
|
<data key="VH">2</data>
|
||||||
|
<data key="VT">PM</data>
|
||||||
|
</node>
|
||||||
|
<edge id="e0" source="n0" target="n1">
|
||||||
|
</edge>
|
||||||
|
<edge id="e1" source="n1" target="n2">
|
||||||
|
</edge>
|
||||||
|
</graph>
|
||||||
|
</graphml>
|
||||||
@@ -55,13 +55,13 @@
|
|||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
<Option Name="WTXSimExportSim" Val="5"/>
|
<Option Name="WTXSimExportSim" Val="6"/>
|
||||||
<Option Name="WTModelSimExportSim" Val="5"/>
|
<Option Name="WTModelSimExportSim" Val="6"/>
|
||||||
<Option Name="WTQuestaExportSim" Val="5"/>
|
<Option Name="WTQuestaExportSim" Val="6"/>
|
||||||
<Option Name="WTIesExportSim" Val="5"/>
|
<Option Name="WTIesExportSim" Val="6"/>
|
||||||
<Option Name="WTVcsExportSim" Val="5"/>
|
<Option Name="WTVcsExportSim" Val="6"/>
|
||||||
<Option Name="WTRivieraExportSim" Val="5"/>
|
<Option Name="WTRivieraExportSim" Val="6"/>
|
||||||
<Option Name="WTActivehdlExportSim" Val="5"/>
|
<Option Name="WTActivehdlExportSim" Val="6"/>
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
@@ -77,6 +77,12 @@
|
|||||||
<FileSets Version="1" Minor="31">
|
<FileSets Version="1" Minor="31">
|
||||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
<Filter Type="Srcs"/>
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PPRDIR/../../src/bram_controller.vhd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/bram_writer.vhd">
|
<File Path="$PPRDIR/../../src/bram_writer.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
@@ -119,30 +125,22 @@
|
|||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/lab_2/lab_2.bd">
|
<File Path="$PPRDIR/../../design/lab_2/lab_2.bd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/lab_2/hdl/lab_2_wrapper.vhd">
|
<File Path="$PPRDIR/../../design/lab_2/hdl/lab_2_wrapper.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/bram_controller.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
<Config>
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
<Option Name="TopModule" Val="lab_2_wrapper"/>
|
<Option Name="TopModule" Val="lab_2_wrapper"/>
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
@@ -161,8 +159,10 @@
|
|||||||
<Filter Type="Srcs"/>
|
<Filter Type="Srcs"/>
|
||||||
<Config>
|
<Config>
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
<Option Name="TopModule" Val="lab_2_wrapper"/>
|
<Option Name="TopModule" Val="bram_writer"/>
|
||||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopArchitecture" Val="rtl"/>
|
||||||
|
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/bram_writer.vhd"/>
|
||||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
<Option Name="TransportPathDelay" Val="0"/>
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
<Option Name="TransportIntDelay" Val="0"/>
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
|||||||
@@ -55,13 +55,13 @@
|
|||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
<Option Name="WTXSimExportSim" Val="1"/>
|
<Option Name="WTXSimExportSim" Val="3"/>
|
||||||
<Option Name="WTModelSimExportSim" Val="1"/>
|
<Option Name="WTModelSimExportSim" Val="3"/>
|
||||||
<Option Name="WTQuestaExportSim" Val="1"/>
|
<Option Name="WTQuestaExportSim" Val="3"/>
|
||||||
<Option Name="WTIesExportSim" Val="1"/>
|
<Option Name="WTIesExportSim" Val="3"/>
|
||||||
<Option Name="WTVcsExportSim" Val="1"/>
|
<Option Name="WTVcsExportSim" Val="3"/>
|
||||||
<Option Name="WTRivieraExportSim" Val="1"/>
|
<Option Name="WTRivieraExportSim" Val="3"/>
|
||||||
<Option Name="WTActivehdlExportSim" Val="1"/>
|
<Option Name="WTActivehdlExportSim" Val="3"/>
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
@@ -89,29 +89,23 @@
|
|||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/pak_depak/pak_depak.bd">
|
<File Path="$PPRDIR/../../design/pak_depak/pak_depak.bd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/pak_depak/hdl/pak_depak_wrapper.vhd">
|
<File Path="$PPRDIR/../../design/pak_depak/hdl/pak_depak_wrapper.vhd">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
<File Path="$PPRDIR/../../src/fifo.vhd">
|
|
||||||
<FileInfo>
|
|
||||||
<Attr Name="AutoDisabled" Val="1"/>
|
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
|
||||||
</FileInfo>
|
|
||||||
</File>
|
|
||||||
<Config>
|
<Config>
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
<Option Name="TopModule" Val="pak_depak_wrapper"/>
|
<Option Name="TopModule" Val="pak_depak_wrapper"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
|||||||
Reference in New Issue
Block a user