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Refactor rgb2gray and divider_by_3: update signal handling, enhance state management, and improve stimulus memory for better functionality and clarity

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Davide Cavagnola
2025-04-24 11:25:39 +02:00
parent 5995a532f5
commit 75fb66e531
3 changed files with 126 additions and 120 deletions
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18
LAB2/sim/tb_rgb2gray.vhd
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@@ -43,15 +43,15 @@ ARCHITECTURE Behavioral OF rgb2gray_tb IS
-- Stimulus memory for RGB triplets (R, G, B) -- Stimulus memory for RGB triplets (R, G, B)
TYPE rgb_mem_type IS ARRAY(0 TO 8, 0 TO 2) OF STD_LOGIC_VECTOR(7 DOWNTO 0); TYPE rgb_mem_type IS ARRAY(0 TO 8, 0 TO 2) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rgb_mem : rgb_mem_type := ( SIGNAL rgb_mem : rgb_mem_type := (
(x"10", x"20", x"30"), (x"1A", x"2F", x"7C"),
(x"40", x"50", x"60"), (x"05", x"7F", x"3B"),
(x"70", x"80", x"90"), (x"4D", x"12", x"6E"),
(x"A0", x"B0", x"C0"), (x"7E", x"01", x"23"),
(x"D0", x"E0", x"F0"), (x"3C", x"55", x"7A"),
(x"01", x"02", x"03"), (x"2B", x"0F", x"6D"),
(x"04", x"05", x"06"), (x"7B", x"7D", x"7C"),
(x"07", x"08", x"09"), (x"6A", x"3E", x"27"),
(x"0A", x"0B", x"0C") (x"0C", x"5A", x"7F")
); );
SIGNAL tready_block_req : STD_LOGIC := '0'; SIGNAL tready_block_req : STD_LOGIC := '0';

3
LAB2/src/divider_by_3.vhd
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@@ -36,6 +36,9 @@ BEGIN
-- 4. The final grayscale value is extracted from the result and converted back to a std_logic_vector. -- 4. The final grayscale value is extracted from the result and converted back to a std_logic_vector.
-- Calculate the sum of the RGB channels -- Calculate the sum of the RGB channels
-- The addition of 2 is used to implement rounding when dividing by 3.
-- This is a common technique: adding half of the divisor (3/2 ? 2) before division
-- ensures that the result is rounded to the nearest integer instead of truncated.
sum_extended <= dividend + TO_UNSIGNED(2, BIT_DEPTH + 2); sum_extended <= dividend + TO_UNSIGNED(2, BIT_DEPTH + 2);
-- Multiply the sum by the precomputed multiplier -- Multiply the sum by the precomputed multiplier

225
LAB2/src/rgb2gray.vhd
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@@ -3,136 +3,139 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL; USE IEEE.NUMERIC_STD.ALL;
ENTITY rgb2gray IS ENTITY rgb2gray IS
PORT ( PORT (
clk : IN STD_LOGIC; clk : IN STD_LOGIC;
resetn : IN STD_LOGIC; resetn : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC; m_axis_tvalid : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tready : IN STD_LOGIC; m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC; m_axis_tlast : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC; s_axis_tvalid : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tready : OUT STD_LOGIC; s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC s_axis_tlast : IN STD_LOGIC
); );
END rgb2gray; END rgb2gray;
ARCHITECTURE Behavioral OF rgb2gray IS ARCHITECTURE Behavioral OF rgb2gray IS
COMPONENT divider_by_3 COMPONENT divider_by_3
GENERIC ( GENERIC (
BIT_DEPTH : INTEGER := 7 BIT_DEPTH : INTEGER := 7
); );
PORT ( PORT (
dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0); dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0) result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
); );
END COMPONENT; END COMPONENT;
TYPE state_type IS (WAIT_R, WAIT_G, WAIT_B); TYPE state_type IS (IDLE, ACCUMULATE, WAIT_DIV, SEND);
SIGNAL state : state_type := WAIT_R; SIGNAL state : state_type := IDLE;
SIGNAL r_val, g_val : UNSIGNED(7 DOWNTO 0); SIGNAL sum : UNSIGNED(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL sum : UNSIGNED(8 DOWNTO 0); SIGNAL rgb_sum : UNSIGNED(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL gray : UNSIGNED(6 DOWNTO 0); SIGNAL gray : UNSIGNED(6 DOWNTO 0);
SIGNAL count : INTEGER RANGE 0 TO 2 := 0;
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0'; SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC := '0'; SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tlast_int : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC := '1';
SIGNAL trigger : STD_LOGIC := '0'; SIGNAL last_seen : STD_LOGIC := '0';
SIGNAL last_seen : STD_LOGIC := '0';
BEGIN BEGIN
s_axis_tready <= s_axis_tready_int; s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int; m_axis_tvalid <= m_axis_tvalid_int;
m_axis_tdata <= m_axis_tdata_int;
m_axis_tlast <= m_axis_tlast_int;
-- Divider instance -- Divider instance
DIVIDER : divider_by_3 DIVIDER : divider_by_3
GENERIC MAP( GENERIC MAP(
BIT_DEPTH => 7 BIT_DEPTH => 7
) )
PORT MAP( PORT MAP(
dividend => sum, dividend => rgb_sum,
result => gray result => gray
); );
PROCESS (clk) PROCESS (clk)
BEGIN BEGIN
IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF resetn = '0' THEN IF resetn = '0' THEN
-- Reset all signals state <= IDLE;
state <= WAIT_R; sum <= (OTHERS => '0');
rgb_sum <= (OTHERS => '0');
count <= 0;
m_axis_tvalid_int <= '0';
m_axis_tdata_int <= (OTHERS => '0');
m_axis_tlast_int <= '0';
s_axis_tready_int <= '1';
last_seen <= '0';
ELSE
-- Default assignments
m_axis_tlast_int <= '0';
s_axis_tready_int <= '0'; CASE state IS
m_axis_tvalid_int <= '0'; WHEN IDLE =>
m_axis_tdata_int <= (OTHERS => '0');
sum <= (OTHERS => '0');
count <= 0;
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= unsigned('0' & s_axis_tdata);
count <= 1;
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
state <= ACCUMULATE;
END IF;
m_axis_tdata <= (OTHERS => '0'); WHEN ACCUMULATE =>
m_axis_tlast <= '0'; IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= sum + unsigned(s_axis_tdata);
IF count = 2 THEN
rgb_sum <= sum + unsigned(s_axis_tdata);
s_axis_tready_int <= '0';
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
state <= WAIT_DIV;
ELSE
count <= count + 1;
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
END IF;
END IF;
r_val <= (OTHERS => '0'); WHEN WAIT_DIV =>
g_val <= (OTHERS => '0'); -- Ora gray <20> valido
m_axis_tdata_int <= '0' & STD_LOGIC_VECTOR(gray);
m_axis_tvalid_int <= '1';
s_axis_tready_int <= '0';
IF last_seen = '1' THEN
m_axis_tlast_int <= '1';
last_seen <= '0';
END IF;
state <= SEND;
sum <= (OTHERS => '0'); WHEN SEND =>
-- Mantieni il dato finch<63> non viene accettato
IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';
state <= IDLE;
END IF;
trigger <= '0'; END CASE;
END IF;
ELSE END IF;
END PROCESS;
-- Input data - slave
s_axis_tready_int <= m_axis_tready;
IF s_axis_tlast = '1' THEN
last_seen <= '1';
ELSE
m_axis_tlast <= '0';
END IF;
-- Output data - master
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= '0' & STD_LOGIC_VECTOR(gray); -- MSB zero + 7bit gray
IF last_seen = '1' THEN
m_axis_tlast <= '1';
last_seen <= '0';
END IF;
trigger <= '0';
END IF;
-- State machine for R, G, B values buffering
CASE state IS
WHEN WAIT_R =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
r_val <= unsigned(s_axis_tdata);
state <= WAIT_G;
END IF;
WHEN WAIT_G =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
g_val <= unsigned(s_axis_tdata);
state <= WAIT_B;
END IF;
WHEN WAIT_B =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= RESIZE(r_val + g_val + unsigned(s_axis_tdata), sum'length);
trigger <= '1';
state <= WAIT_R;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE; END ARCHITECTURE;