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Refactor and update various components in LAB2 design

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- Updated node connections in lab_2.bda and pak_depak.bda to correct source and target references.
- Modified pak_depak_wrapper.vhd to reflect the correct timestamp.
- Rearranged the order of components in pak_depak.bd for clarity and consistency.
- Adjusted BRAM writer logic in bram_writer.vhd for improved data handling and comments for clarity.
- Enhanced depacketizer.vhd with additional comments and logic adjustments for better data reception.
- Refined divider_by_3.vhd to optimize division calculations and improve clarity in comments.
- Improved img_conv.vhd with better state management and comments for the convolution process.
- Updated led_blinker.vhd to enhance readability and maintainability with clearer comments.
- Enhanced packetizer.vhd to improve data handling and added comments for better understanding.
- Adjusted rgb2gray.vhd to include standard library comments for consistency.
- Updated test.py to improve image processing logic and added visualization for differences.
- Added new binary files for test_nopath.exe and archived project files for lab2 and pak_depak.
- Updated Vivado project files to ensure correct paths and settings for synthesis and implementation.
This commit is contained in:
Davide Cavagnola
2025-04-25 00:43:10 +02:00
parent 5cabb20fdd
commit 835b4d0ab8
21 changed files with 535 additions and 470 deletions
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4
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
View File

@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Tue Apr 22 22:53:03 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Date : Fri Apr 25 00:08:55 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper
--Purpose : IP block netlist

266
LAB2/design/lab_2/lab_2.bd
View File

@@ -14,13 +14,13 @@
"clk_wiz_0": "",
"proc_sys_reset_1": "",
"AXI4Stream_UART_0": "",
"bram_writer_0": "",
"packetizer_0": "",
"led_blinker_0": "",
"led_blinker_1": "",
"led_blinker_2": "",
"img_conv_0": "",
"depacketizer_0": "",
"packetizer_0": "",
"bram_writer_0": "",
"rgb2gray_0": ""
},
"interface_ports": {
@@ -80,8 +80,8 @@
"components": {
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"xci_name": "lab_2_system_ila_0_1",
"xci_path": "ip\\lab_2_system_ila_0_1\\lab_2_system_ila_0_1.xci",
"xci_name": "lab_2_system_ila_0_0",
"xci_path": "ip\\lab_2_system_ila_0_0\\lab_2_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_MON_TYPE": {
@@ -123,8 +123,8 @@
},
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "lab_2_clk_wiz_0_1",
"xci_path": "ip\\lab_2_clk_wiz_0_1\\lab_2_clk_wiz_0_1.xci",
"xci_name": "lab_2_clk_wiz_0_0",
"xci_path": "ip\\lab_2_clk_wiz_0_0\\lab_2_clk_wiz_0_0.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
@@ -140,8 +140,8 @@
},
"proc_sys_reset_1": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "lab_2_proc_sys_reset_1_1",
"xci_path": "ip\\lab_2_proc_sys_reset_1_1\\lab_2_proc_sys_reset_1_1.xci",
"xci_name": "lab_2_proc_sys_reset_1_0",
"xci_path": "ip\\lab_2_proc_sys_reset_1_0\\lab_2_proc_sys_reset_1_0.xci",
"inst_hier_path": "proc_sys_reset_1",
"parameters": {
"RESET_BOARD_INTERFACE": {
@@ -154,8 +154,8 @@
},
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "lab_2_AXI4Stream_UART_0_2",
"xci_path": "ip\\lab_2_AXI4Stream_UART_0_2\\lab_2_AXI4Stream_UART_0_2.xci",
"xci_name": "lab_2_AXI4Stream_UART_0_0",
"xci_path": "ip\\lab_2_AXI4Stream_UART_0_0\\lab_2_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BOARD_INTERFACE": {
@@ -166,17 +166,83 @@
}
}
},
"bram_writer_0": {
"vlnv": "xilinx.com:module_ref:bram_writer:1.0",
"xci_name": "lab_2_bram_writer_0_0",
"xci_path": "ip\\lab_2_bram_writer_0_0\\lab_2_bram_writer_0_0.xci",
"inst_hier_path": "bram_writer_0",
"packetizer_0": {
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
"xci_name": "lab_2_packetizer_0_0",
"xci_path": "ip\\lab_2_packetizer_0_0\\lab_2_packetizer_0_0.xci",
"inst_hier_path": "packetizer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "bram_writer",
"ref_name": "packetizer",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
@@ -254,7 +320,7 @@
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "s_axis",
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
@@ -284,31 +350,6 @@
"value_src": "constant"
}
}
},
"conv_addr": {
"direction": "I",
"left": "15",
"right": "0"
},
"conv_data": {
"direction": "O",
"left": "6",
"right": "0"
},
"start_conv": {
"direction": "O"
},
"done_conv": {
"direction": "I"
},
"write_ok": {
"direction": "O"
},
"overflow": {
"direction": "O"
},
"underflow": {
"direction": "O"
}
}
},
@@ -789,83 +830,17 @@
}
}
},
"packetizer_0": {
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
"xci_name": "lab_2_packetizer_0_0",
"xci_path": "ip\\lab_2_packetizer_0_0\\lab_2_packetizer_0_0.xci",
"inst_hier_path": "packetizer_0",
"bram_writer_0": {
"vlnv": "xilinx.com:module_ref:bram_writer:1.0",
"xci_name": "lab_2_bram_writer_0_0",
"xci_path": "ip\\lab_2_bram_writer_0_0\\lab_2_bram_writer_0_0.xci",
"inst_hier_path": "bram_writer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "packetizer",
"ref_name": "bram_writer",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
@@ -943,7 +918,7 @@
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value": "s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
@@ -973,6 +948,31 @@
"value_src": "constant"
}
}
},
"conv_addr": {
"direction": "I",
"left": "15",
"right": "0"
},
"conv_data": {
"direction": "O",
"left": "6",
"right": "0"
},
"start_conv": {
"direction": "O"
},
"done_conv": {
"direction": "I"
},
"write_ok": {
"direction": "O"
},
"overflow": {
"direction": "O"
},
"underflow": {
"direction": "O"
}
}
},
@@ -1169,6 +1169,20 @@
}
},
"interface_nets": {
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
},
"img_conv_0_m_axis": {
"interface_ports": [
"img_conv_0/m_axis",
@@ -1188,20 +1202,6 @@
"depacketizer_0/s_axis"
]
},
"Conn": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"rgb2gray_0_m_axis": {
"interface_ports": [
"rgb2gray_0/m_axis",
"bram_writer_0/s_axis",
"system_ila_0/SLOT_2_AXIS"
]
},
"packetizer_0_m_axis": {
"interface_ports": [
"packetizer_0/m_axis",
@@ -1218,13 +1218,13 @@
"AXI4Stream_UART_0/clk_uart",
"AXI4Stream_UART_0/m00_axis_rx_aclk",
"AXI4Stream_UART_0/s00_axis_tx_aclk",
"bram_writer_0/clk",
"packetizer_0/clk",
"led_blinker_0/clk",
"led_blinker_1/clk",
"led_blinker_2/clk",
"img_conv_0/clk",
"depacketizer_0/clk",
"packetizer_0/clk",
"bram_writer_0/clk",
"rgb2gray_0/clk"
]
},
@@ -1234,13 +1234,13 @@
"system_ila_0/resetn",
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
"bram_writer_0/aresetn",
"packetizer_0/aresetn",
"led_blinker_0/aresetn",
"led_blinker_1/aresetn",
"led_blinker_2/aresetn",
"img_conv_0/aresetn",
"depacketizer_0/aresetn",
"packetizer_0/aresetn",
"bram_writer_0/aresetn",
"rgb2gray_0/resetn"
]
},

12
LAB2/design/lab_2/lab_2.bda
View File

@@ -26,17 +26,17 @@
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n0" target="n1">
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>