feat: Add initial LAB2-3 project presentation and areas for improvement

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2025-07-13 18:02:44 +02:00
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# LAB2 Project Presentation
## Project Description
The LAB2 project consists of the design and implementation of a digital system for image processing and data communication. The system is composed of several functional blocks, each responsible for a specific task in the processing pipeline. The main objectives are:
- Receive and process image data
- Perform color space conversion (e.g., RGB to grayscale)
- Apply convolution filters to the image
- Packetize the processed data for transmission
- Support loopback and test modes for verification
## Block Diagram
Below is a conceptual block diagram of the LAB2 system:
```mermaid
flowchart LR
IN[PC] -.-> UART[UART]
UART -.-> IN
UART --> DEPACK[Depack]
DEPACK --> C2G[Color to Grayscale Converter]
C2G --> BRAM[BRAM Writer]
BRAM --> Underflow
BRAM -->Overflow
BRAM -->Ok
BRAM <-.-> CONV[Convolution Filter]
BRAM <-.-> CONV
CONV --> PACK[Packetizer]
PACK --> UART
```
## Areas for Improvement
- In loopback mode, when sending an empty packet (FFF1), the module temporarily stores H and F and prepends them to the header of the next packet. There is an error in the pack/depack logic.
- The implementation of the depacketizer is complex, and the precise error has not been identified.
- The color conversion (C2G) uses a divider by 3, but the approximation method is unclear (it sums half of the power-of-two factor used in the divider—why?). -> Just add comments explainig how it works
- Convolution is performed with various unconstrained integers.
- In general, the VHDL code is somewhat complex, although generally correct. Aim to simplify and make the code more readable.

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# LAB3 Project Presentation
## Project Description
*To be completed: Add a description of the LAB3 project here.*
## Block Diagram
*To be completed: Add a block diagram of the LAB3 system here (e.g., using Mermaid or an image).*
## Areas for Improvement
- JSTK: Non-atomicity in writing to the RGB LED; the rest is well done and clear.
- Mute: (IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN) AXIS error; s_axis_tready should be checked. The original would be correct if s_axis_tready was directly connected to m_axis_tready. As written, it waits for ready to assert valid.
- Volume controller: Waits for ready to assert valid (IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN).
- Balance: (IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN) AXI condition is incorrect; the rest is correct.