Add initial implementations for various audio processing components
- Created LFO entity for low-frequency oscillation control. - Added all_pass_filter entity for signal processing. - Implemented balance_controller for audio balance adjustments. - Developed debouncer to stabilize input signals. - Introduced digilent_jstk2 for joystick data handling. - Added edge_detector_toggle for edge detection functionality. - Created effect_selector to manage audio effects based on joystick input. - Implemented jstk_uart_bridge for communication between joystick and UART. - Developed led_controller for LED management. - Introduced led_level_controller for controlling multiple LEDs. - Created moving_average_filter for smoothing input signals. - Added moving_average_filter_en with enable functionality. - Implemented mute_controller to handle mute functionality. - Developed volume_controller for volume adjustments. - Introduced volume_multiplier for scaling audio signals. - Created volume_saturator to ensure audio signals stay within bounds.
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LAB3/src/led_level_controller.vhd
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60
LAB3/src/led_level_controller.vhd
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 22.05.2021 15:42:35
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-- Design Name:
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-- Module Name: led_level_controller - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity led_level_controller is
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generic(
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NUM_LEDS : positive := 16;
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CHANNEL_LENGHT : positive := 24;
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refresh_time_ms: positive :=1;
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clock_period_ns: positive :=10
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);
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Port (
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aclk : in std_logic;
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aresetn : in std_logic;
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led : out std_logic_vector(NUM_LEDS-1 downto 0);
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s_axis_tvalid : in std_logic;
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s_axis_tdata : in std_logic_vector(CHANNEL_LENGHT-1 downto 0);
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s_axis_tlast : in std_logic;
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s_axis_tready : out std_logic
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);
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end led_level_controller;
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architecture Behavioral of led_level_controller is
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begin
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end Behavioral;
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