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Add AXI4-Stream UART IP and associated files

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- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.
This commit is contained in:
Davide Cavagnola
2025-05-12 18:16:58 +02:00
parent a4ec7ce43a
commit b11c65043f
20 changed files with 3906 additions and 6 deletions
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673
LAB3/design/diligent_jstk/diligent_jstk.bd Normal file
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{
"design": {
"design_info": {
"boundary_crc": "0x7CDC72F2E486A675",
"device": "xc7a35tcpg236-1",
"name": "diligent_jstk",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "None",
"tool_version": "2020.2",
"validated": "true"
},
"design_tree": {
"proc_sys_reset_0": "",
"clk_wiz_0": "",
"AXI4Stream_UART_0": "",
"digilent_jstk2_0": "",
"jstk_uart_bridge_0": "",
"axi4stream_spi_master_0": ""
},
"interface_ports": {
"usb_uart": {
"mode": "Master",
"vlnv": "xilinx.com:interface:uart_rtl:1.0"
},
"SPI_M_0": {
"mode": "Master",
"vlnv": "xilinx.com:interface:spi_rtl:1.0"
}
},
"ports": {
"reset": {
"type": "rst",
"direction": "I",
"parameters": {
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"POLARITY": {
"value": "ACTIVE_HIGH"
}
}
},
"sys_clock": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "diligent_jstk_sys_clock",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000"
}
}
}
},
"components": {
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "diligent_jstk_proc_sys_reset_0_0",
"xci_path": "ip\\diligent_jstk_proc_sys_reset_0_0\\diligent_jstk_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
"value": "reset"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "diligent_jstk_clk_wiz_0_1",
"xci_path": "ip\\diligent_jstk_clk_wiz_0_1\\diligent_jstk_clk_wiz_0_1.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
"value": "sys_clock"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "diligent_jstk_AXI4Stream_UART_0_0",
"xci_path": "ip\\diligent_jstk_AXI4Stream_UART_0_0\\diligent_jstk_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BOARD_INTERFACE": {
"value": "usb_uart"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "diligent_jstk_digilent_jstk2_0_0",
"xci_path": "ip\\diligent_jstk_digilent_jstk2_0_0\\diligent_jstk_digilent_jstk2_0_0.xci",
"inst_hier_path": "digilent_jstk2_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "digilent_jstk2",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "0",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
}
}
}
},
"ports": {
"aclk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"jstk_x": {
"direction": "O",
"left": "9",
"right": "0"
},
"jstk_y": {
"direction": "O",
"left": "9",
"right": "0"
},
"btn_jstk": {
"direction": "O"
},
"btn_trigger": {
"direction": "O"
},
"led_r": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_g": {
"direction": "I",
"left": "7",
"right": "0"
},
"led_b": {
"direction": "I",
"left": "7",
"right": "0"
}
}
},
"jstk_uart_bridge_0": {
"vlnv": "xilinx.com:module_ref:jstk_uart_bridge:1.0",
"xci_name": "diligent_jstk_jstk_uart_bridge_0_0",
"xci_path": "ip\\diligent_jstk_jstk_uart_bridge_0_0\\diligent_jstk_jstk_uart_bridge_0_0.xci",
"inst_hier_path": "jstk_uart_bridge_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "jstk_uart_bridge",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"aclk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
},
"jstk_x": {
"direction": "I",
"left": "9",
"right": "0"
},
"jstk_y": {
"direction": "I",
"left": "9",
"right": "0"
},
"btn_jstk": {
"direction": "I"
},
"btn_trigger": {
"direction": "I"
},
"led_r": {
"direction": "O",
"left": "7",
"right": "0"
},
"led_g": {
"direction": "O",
"left": "7",
"right": "0"
},
"led_b": {
"direction": "O",
"left": "7",
"right": "0"
}
}
},
"axi4stream_spi_master_0": {
"vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
"xci_name": "diligent_jstk_axi4stream_spi_master_0_0",
"xci_path": "ip\\diligent_jstk_axi4stream_spi_master_0_0\\diligent_jstk_axi4stream_spi_master_0_0.xci",
"inst_hier_path": "axi4stream_spi_master_0"
}
},
"interface_nets": {
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
}
},
"nets": {
"reset_1": {
"ports": [
"reset",
"proc_sys_reset_0/ext_reset_in",
"clk_wiz_0/reset"
]
},
"sys_clock_1": {
"ports": [
"sys_clock",
"clk_wiz_0/clk_in1"
]
},
"clk_wiz_0_locked": {
"ports": [
"clk_wiz_0/locked",
"proc_sys_reset_0/dcm_locked"
]
},
"clk_wiz_0_clk_out1": {
"ports": [
"clk_wiz_0/clk_out1",
"proc_sys_reset_0/slowest_sync_clk",
"axi4stream_spi_master_0/aclk",
"digilent_jstk2_0/aclk",
"AXI4Stream_UART_0/clk_uart",
"AXI4Stream_UART_0/m00_axis_rx_aclk",
"jstk_uart_bridge_0/aclk",
"AXI4Stream_UART_0/s00_axis_tx_aclk"
]
},
"digilent_jstk2_0_btn_trigger": {
"ports": [
"digilent_jstk2_0/btn_trigger",
"jstk_uart_bridge_0/btn_trigger"
]
},
"digilent_jstk2_0_btn_jstk": {
"ports": [
"digilent_jstk2_0/btn_jstk",
"jstk_uart_bridge_0/btn_jstk"
]
},
"digilent_jstk2_0_jstk_y": {
"ports": [
"digilent_jstk2_0/jstk_y",
"jstk_uart_bridge_0/jstk_y"
]
},
"digilent_jstk2_0_jstk_x": {
"ports": [
"digilent_jstk2_0/jstk_x",
"jstk_uart_bridge_0/jstk_x"
]
},
"jstk_uart_bridge_0_led_r": {
"ports": [
"jstk_uart_bridge_0/led_r",
"digilent_jstk2_0/led_r"
]
},
"jstk_uart_bridge_0_led_g": {
"ports": [
"jstk_uart_bridge_0/led_g",
"digilent_jstk2_0/led_g"
]
},
"jstk_uart_bridge_0_led_b": {
"ports": [
"jstk_uart_bridge_0/led_b",
"digilent_jstk2_0/led_b"
]
},
"proc_sys_reset_0_peripheral_aresetn": {
"ports": [
"proc_sys_reset_0/peripheral_aresetn",
"digilent_jstk2_0/aresetn",
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
"jstk_uart_bridge_0/aresetn",
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
"axi4stream_spi_master_0/aresetn"
]
},
"proc_sys_reset_0_peripheral_reset": {
"ports": [
"proc_sys_reset_0/peripheral_reset",
"AXI4Stream_UART_0/rst"
]
}
}
}
}

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LAB3/design/diligent_jstk/diligent_jstk.bda Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
</edge>
<edge id="e1" source="n0" target="n1">
</edge>
</graph>
</graphml>

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LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd Normal file
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon May 12 15:44:44 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity diligent_jstk_wrapper is
port (
SPI_M_0_io0_io : inout STD_LOGIC;
SPI_M_0_io1_io : inout STD_LOGIC;
SPI_M_0_sck_io : inout STD_LOGIC;
SPI_M_0_ss_io : inout STD_LOGIC;
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end diligent_jstk_wrapper;
architecture STRUCTURE of diligent_jstk_wrapper is
component diligent_jstk is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
SPI_M_0_sck_t : out STD_LOGIC;
SPI_M_0_io1_o : out STD_LOGIC;
SPI_M_0_ss_t : out STD_LOGIC;
SPI_M_0_io0_o : out STD_LOGIC;
SPI_M_0_sck_i : in STD_LOGIC;
SPI_M_0_ss_o : out STD_LOGIC;
SPI_M_0_io0_t : out STD_LOGIC;
SPI_M_0_io1_t : out STD_LOGIC;
SPI_M_0_sck_o : out STD_LOGIC;
SPI_M_0_ss_i : in STD_LOGIC;
SPI_M_0_io1_i : in STD_LOGIC;
SPI_M_0_io0_i : in STD_LOGIC
);
end component diligent_jstk;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal SPI_M_0_io0_i : STD_LOGIC;
signal SPI_M_0_io0_o : STD_LOGIC;
signal SPI_M_0_io0_t : STD_LOGIC;
signal SPI_M_0_io1_i : STD_LOGIC;
signal SPI_M_0_io1_o : STD_LOGIC;
signal SPI_M_0_io1_t : STD_LOGIC;
signal SPI_M_0_sck_i : STD_LOGIC;
signal SPI_M_0_sck_o : STD_LOGIC;
signal SPI_M_0_sck_t : STD_LOGIC;
signal SPI_M_0_ss_i : STD_LOGIC;
signal SPI_M_0_ss_o : STD_LOGIC;
signal SPI_M_0_ss_t : STD_LOGIC;
begin
SPI_M_0_io0_iobuf: component IOBUF
port map (
I => SPI_M_0_io0_o,
IO => SPI_M_0_io0_io,
O => SPI_M_0_io0_i,
T => SPI_M_0_io0_t
);
SPI_M_0_io1_iobuf: component IOBUF
port map (
I => SPI_M_0_io1_o,
IO => SPI_M_0_io1_io,
O => SPI_M_0_io1_i,
T => SPI_M_0_io1_t
);
SPI_M_0_sck_iobuf: component IOBUF
port map (
I => SPI_M_0_sck_o,
IO => SPI_M_0_sck_io,
O => SPI_M_0_sck_i,
T => SPI_M_0_sck_t
);
SPI_M_0_ss_iobuf: component IOBUF
port map (
I => SPI_M_0_ss_o,
IO => SPI_M_0_ss_io,
O => SPI_M_0_ss_i,
T => SPI_M_0_ss_t
);
diligent_jstk_i: component diligent_jstk
port map (
SPI_M_0_io0_i => SPI_M_0_io0_i,
SPI_M_0_io0_o => SPI_M_0_io0_o,
SPI_M_0_io0_t => SPI_M_0_io0_t,
SPI_M_0_io1_i => SPI_M_0_io1_i,
SPI_M_0_io1_o => SPI_M_0_io1_o,
SPI_M_0_io1_t => SPI_M_0_io1_t,
SPI_M_0_sck_i => SPI_M_0_sck_i,
SPI_M_0_sck_o => SPI_M_0_sck_o,
SPI_M_0_sck_t => SPI_M_0_sck_t,
SPI_M_0_ss_i => SPI_M_0_ss_i,
SPI_M_0_ss_o => SPI_M_0_ss_o,
SPI_M_0_ss_t => SPI_M_0_ss_t,
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
end STRUCTURE;