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Add AXI4-Stream UART IP and associated files

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- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.
This commit is contained in:
Davide Cavagnola
2025-05-12 18:16:58 +02:00
parent a4ec7ce43a
commit b11c65043f
20 changed files with 3906 additions and 6 deletions
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12
LAB3/design/lab_3/lab_3.bda
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@@ -26,17 +26,17 @@
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