Add AXI4-Stream UART IP and associated files
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
This commit is contained in:
58
LAB3/design/loopback_I2S/hdl/loopback_I2S_wrapper.vhd
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58
LAB3/design/loopback_I2S/hdl/loopback_I2S_wrapper.vhd
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@@ -0,0 +1,58 @@
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------
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--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
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--Date : Mon May 12 18:14:19 2025
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--Host : Davide-Samsung running 64-bit major release (build 9200)
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--Command : generate_target loopback_I2S_wrapper.bd
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--Design : loopback_I2S_wrapper
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--Purpose : IP block netlist
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library UNISIM;
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use UNISIM.VCOMPONENTS.ALL;
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entity loopback_I2S_wrapper is
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port (
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reset : in STD_LOGIC;
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rx_lrck_0 : out STD_LOGIC;
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rx_mclk_0 : out STD_LOGIC;
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rx_sclk_0 : out STD_LOGIC;
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rx_sdin_0 : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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tx_lrck_0 : out STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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tx_sclk_0 : out STD_LOGIC;
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tx_sdout_0 : out STD_LOGIC
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);
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end loopback_I2S_wrapper;
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architecture STRUCTURE of loopback_I2S_wrapper is
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component loopback_I2S is
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port (
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reset : in STD_LOGIC;
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sys_clock : in STD_LOGIC;
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rx_sdin_0 : in STD_LOGIC;
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tx_mclk_0 : out STD_LOGIC;
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tx_lrck_0 : out STD_LOGIC;
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tx_sclk_0 : out STD_LOGIC;
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tx_sdout_0 : out STD_LOGIC;
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rx_mclk_0 : out STD_LOGIC;
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rx_lrck_0 : out STD_LOGIC;
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rx_sclk_0 : out STD_LOGIC
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);
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end component loopback_I2S;
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begin
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loopback_I2S_i: component loopback_I2S
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port map (
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reset => reset,
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rx_lrck_0 => rx_lrck_0,
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rx_mclk_0 => rx_mclk_0,
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rx_sclk_0 => rx_sclk_0,
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rx_sdin_0 => rx_sdin_0,
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sys_clock => sys_clock,
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tx_lrck_0 => tx_lrck_0,
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tx_mclk_0 => tx_mclk_0,
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tx_sclk_0 => tx_sclk_0,
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tx_sdout_0 => tx_sdout_0
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);
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end STRUCTURE;
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288
LAB3/design/loopback_I2S/loopback_I2S.bd
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288
LAB3/design/loopback_I2S/loopback_I2S.bd
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@@ -0,0 +1,288 @@
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{
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"design": {
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"design_info": {
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"boundary_crc": "0x82F7CD001DE2BC1E",
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"device": "xc7a35tcpg236-1",
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"name": "loopback_I2S",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "None",
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"tool_version": "2020.2",
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"validated": "true"
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},
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"design_tree": {
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"proc_sys_reset_0": "",
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"clk_wiz_0": "",
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"proc_sys_reset_1": "",
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"axis_dual_i2s_0": "",
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"system_ila_0": ""
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},
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"ports": {
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"reset": {
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"type": "rst",
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"direction": "I",
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"parameters": {
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"POLARITY": {
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"value": "ACTIVE_HIGH"
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}
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}
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},
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"sys_clock": {
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"type": "clk",
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"direction": "I",
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"parameters": {
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"CLK_DOMAIN": {
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"value": "loopback_I2S_sys_clock",
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"value_src": "default"
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},
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"FREQ_HZ": {
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"value": "100000000"
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},
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"FREQ_TOLERANCE_HZ": {
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"value": "0",
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"value_src": "default"
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},
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"INSERT_VIP": {
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"value": "0",
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"value_src": "default"
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},
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"PHASE": {
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"value": "0.000"
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}
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}
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},
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"rx_sdin_0": {
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"direction": "I"
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},
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"tx_mclk_0": {
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"direction": "O"
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},
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"tx_lrck_0": {
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"direction": "O"
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},
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"tx_sclk_0": {
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"direction": "O"
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},
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"tx_sdout_0": {
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"direction": "O"
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},
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"rx_mclk_0": {
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"direction": "O"
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},
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"rx_lrck_0": {
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"direction": "O"
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},
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"rx_sclk_0": {
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"direction": "O"
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}
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},
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"components": {
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"proc_sys_reset_0": {
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"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
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"xci_name": "loopback_I2S_proc_sys_reset_0_0",
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"xci_path": "ip\\loopback_I2S_proc_sys_reset_0_0\\loopback_I2S_proc_sys_reset_0_0.xci",
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"inst_hier_path": "proc_sys_reset_0",
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"parameters": {
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"RESET_BOARD_INTERFACE": {
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"value": "reset"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"clk_wiz_0": {
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"vlnv": "xilinx.com:ip:clk_wiz:6.0",
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"xci_name": "loopback_I2S_clk_wiz_0_0",
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"xci_path": "ip\\loopback_I2S_clk_wiz_0_0\\loopback_I2S_clk_wiz_0_0.xci",
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"inst_hier_path": "clk_wiz_0",
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"parameters": {
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"CLKOUT1_JITTER": {
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"value": "149.337"
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},
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"CLKOUT1_PHASE_ERROR": {
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"value": "122.577"
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},
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"CLKOUT2_JITTER": {
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"value": "201.826"
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},
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"CLKOUT2_PHASE_ERROR": {
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"value": "122.577"
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},
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"CLKOUT2_REQUESTED_OUT_FREQ": {
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"value": "22.579"
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},
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"CLKOUT2_USED": {
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"value": "true"
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},
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"CLK_IN1_BOARD_INTERFACE": {
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"value": "sys_clock"
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},
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"MMCM_CLKFBOUT_MULT_F": {
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"value": "7.000"
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},
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"MMCM_CLKOUT0_DIVIDE_F": {
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"value": "7.000"
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},
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"MMCM_CLKOUT1_DIVIDE": {
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"value": "31"
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},
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"NUM_OUT_CLKS": {
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"value": "2"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"proc_sys_reset_1": {
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"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
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"xci_name": "loopback_I2S_proc_sys_reset_0_1",
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"xci_path": "ip\\loopback_I2S_proc_sys_reset_0_1\\loopback_I2S_proc_sys_reset_0_1.xci",
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"inst_hier_path": "proc_sys_reset_1",
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"parameters": {
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"RESET_BOARD_INTERFACE": {
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"value": "reset"
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},
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"USE_BOARD_FLOW": {
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"value": "true"
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}
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}
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},
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"axis_dual_i2s_0": {
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"vlnv": "DigiLAB:ip:axis_dual_i2s:1.0",
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"xci_name": "loopback_I2S_axis_dual_i2s_0_0",
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"xci_path": "ip\\loopback_I2S_axis_dual_i2s_0_0\\loopback_I2S_axis_dual_i2s_0_0.xci",
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"inst_hier_path": "axis_dual_i2s_0"
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},
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"system_ila_0": {
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"vlnv": "xilinx.com:ip:system_ila:1.1",
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"xci_name": "loopback_I2S_system_ila_0_0",
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"xci_path": "ip\\loopback_I2S_system_ila_0_0\\loopback_I2S_system_ila_0_0.xci",
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"inst_hier_path": "system_ila_0",
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"parameters": {
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"C_SLOT_0_INTF_TYPE": {
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"value": "xilinx.com:interface:axis_rtl:1.0"
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}
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},
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"interface_ports": {
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"SLOT_0_AXIS": {
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"mode": "Monitor",
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"vlnv": "xilinx.com:interface:axis_rtl:1.0"
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}
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}
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}
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},
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"interface_nets": {
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"axis_dual_i2s_0_m_axis": {
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"interface_ports": [
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"axis_dual_i2s_0/s_axis",
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"axis_dual_i2s_0/m_axis",
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"system_ila_0/SLOT_0_AXIS"
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]
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}
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},
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"nets": {
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"reset_1": {
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"ports": [
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"reset",
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"proc_sys_reset_0/ext_reset_in",
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"clk_wiz_0/reset",
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"proc_sys_reset_1/ext_reset_in"
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]
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},
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"sys_clock_1": {
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"ports": [
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"sys_clock",
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"clk_wiz_0/clk_in1"
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]
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},
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"clk_wiz_0_locked": {
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"ports": [
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"clk_wiz_0/locked",
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"proc_sys_reset_0/dcm_locked",
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"proc_sys_reset_1/dcm_locked"
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]
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},
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"clk_wiz_0_clk_out1": {
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"ports": [
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"clk_wiz_0/clk_out1",
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"system_ila_0/clk",
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"axis_dual_i2s_0/aclk",
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"proc_sys_reset_0/slowest_sync_clk"
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]
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},
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"clk_wiz_0_clk_out2": {
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"ports": [
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"clk_wiz_0/clk_out2",
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"proc_sys_reset_1/slowest_sync_clk",
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"axis_dual_i2s_0/i2s_clk"
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]
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},
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"proc_sys_reset_0_peripheral_aresetn": {
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"ports": [
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"proc_sys_reset_0/peripheral_aresetn",
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"system_ila_0/resetn",
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"axis_dual_i2s_0/aresetn"
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]
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},
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"proc_sys_reset_1_peripheral_aresetn": {
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"ports": [
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"proc_sys_reset_1/peripheral_aresetn",
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"axis_dual_i2s_0/i2s_resetn"
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]
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},
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"rx_sdin_0_1": {
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"ports": [
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"rx_sdin_0",
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"axis_dual_i2s_0/rx_sdin"
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]
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},
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"axis_dual_i2s_0_tx_mclk": {
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"ports": [
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"axis_dual_i2s_0/tx_mclk",
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"tx_mclk_0"
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]
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},
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"axis_dual_i2s_0_tx_lrck": {
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"ports": [
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"axis_dual_i2s_0/tx_lrck",
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"tx_lrck_0"
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]
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},
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"axis_dual_i2s_0_tx_sclk": {
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"ports": [
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"axis_dual_i2s_0/tx_sclk",
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"tx_sclk_0"
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]
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},
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"axis_dual_i2s_0_tx_sdout": {
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"ports": [
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"axis_dual_i2s_0/tx_sdout",
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"tx_sdout_0"
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]
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},
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"axis_dual_i2s_0_rx_mclk": {
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"ports": [
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"axis_dual_i2s_0/rx_mclk",
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"rx_mclk_0"
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]
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},
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"axis_dual_i2s_0_rx_lrck": {
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"ports": [
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"axis_dual_i2s_0/rx_lrck",
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"rx_lrck_0"
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]
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},
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"axis_dual_i2s_0_rx_sclk": {
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"ports": [
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"axis_dual_i2s_0/rx_sclk",
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"rx_sclk_0"
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]
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}
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}
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}
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}
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42
LAB3/design/loopback_I2S/loopback_I2S.bda
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42
LAB3/design/loopback_I2S/loopback_I2S.bda
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@@ -0,0 +1,42 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
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<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
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<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
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<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
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<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
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<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
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<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
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<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
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<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
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<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
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<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
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<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
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<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
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<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
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<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
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<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
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<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
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<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
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<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
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<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
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<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
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<node id="n0">
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<data key="TU">active</data>
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<data key="VH">2</data>
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<data key="VT">PM</data>
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</node>
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<node id="n1">
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<data key="VH">2</data>
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<data key="VM">loopback_I2S</data>
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<data key="VT">VR</data>
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</node>
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<node id="n2">
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<data key="VM">loopback_I2S</data>
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<data key="VT">BC</data>
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</node>
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<edge id="e0" source="n2" target="n1">
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</edge>
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<edge id="e1" source="n1" target="n0">
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</edge>
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</graph>
|
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</graphml>
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