Add AXI4-Stream UART IP and associated files
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
This commit is contained in:
765
LAB3/ip/AXI4-Stream_UART/component.xml
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765
LAB3/ip/AXI4-Stream_UART/component.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>DigiLAB</spirit:vendor>
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<spirit:library>ip</spirit:library>
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<spirit:name>AXI4Stream_UART</spirit:name>
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<spirit:version>1.1</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>M00_AXIS_RX</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
|
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<spirit:master/>
|
||||
<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_tdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_tvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_tready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXIS_TX</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_tdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_tvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_tready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>M00_AXIS_RX_RST</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_aresetn</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>M00_AXIS_RX_CLK</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_aclk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX_CLK.ASSOCIATED_BUSIF">M00_AXIS_RX</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX_CLK.ASSOCIATED_RESET">m00_axis_rx_aresetn</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXIS_TX_RST</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_aresetn</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXIS_TX_CLK</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_aclk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX_CLK.ASSOCIATED_BUSIF">S00_AXIS_TX</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX_CLK.ASSOCIATED_RESET">s00_axis_tx_aresetn</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>reset</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>rst</spirit:name>
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||||
</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>ClockUART</spirit:name>
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<spirit:description>Clock used to calculate the delay for UART</spirit:description>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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||||
<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>clk_uart</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCKUART.ASSOCIATED_BUSIF">UART</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCKUART.ASSOCIATED_RESET">rst</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>UART</spirit:name>
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<spirit:displayName>UART</spirit:displayName>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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<spirit:name>TxD</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>UART_TX</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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||||
<spirit:logicalPort>
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||||
<spirit:name>RxD</spirit:name>
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||||
</spirit:logicalPort>
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||||
<spirit:physicalPort>
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||||
<spirit:name>UART_RX</spirit:name>
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||||
</spirit:physicalPort>
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||||
</spirit:portMap>
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||||
</spirit:portMaps>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.UART.BOARD.ASSOCIATED_PARAM">UART_BOARD_INTERFACE</spirit:value>
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||||
<spirit:vendorExtensions>
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||||
<xilinx:parameterInfo>
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||||
<xilinx:enablement>
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||||
<xilinx:presence>required</xilinx:presence>
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||||
</xilinx:enablement>
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||||
</xilinx:parameterInfo>
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||||
</spirit:vendorExtensions>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:busInterface>
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||||
</spirit:busInterfaces>
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||||
<spirit:model>
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||||
<spirit:views>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
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||||
<spirit:displayName>Synthesis</spirit:displayName>
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||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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||||
<spirit:language>vhdl</spirit:language>
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||||
<spirit:modelName>AXI4Stream_UART_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>47fd635e</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>AXI4Stream_UART_v1_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>47fd635e</spirit:value>
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||||
</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>5514ca69</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>bd_tcl</spirit:name>
|
||||
<spirit:displayName>Block Diagram</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>bd_tcl_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
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<spirit:value>c55a27a0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_utilityxitfiles</spirit:name>
|
||||
<spirit:displayName>Utility XIT/TTCL</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
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||||
<spirit:value>16e75233</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_implementation</spirit:name>
|
||||
<spirit:displayName>Implementation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>5c730a16</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk_uart</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>rst</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>UART_TX</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>UART_RX</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>m00_axis_rx_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
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|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>m00_axis_rx_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>m00_axis_rx_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>m00_axis_rx_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>m00_axis_rx_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s00_axis_tx_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s00_axis_tx_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s00_axis_tx_tready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s00_axis_tx_tdata</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s00_axis_tx_tvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>STD_LOGIC</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>UART_BAUD_RATE</spirit:name>
|
||||
<spirit:displayName>Rs232 Baud Rate</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.UART_BAUD_RATE" spirit:minimum="0" spirit:rangeType="long">115200</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>UART_CLOCK_FREQUENCY</spirit:name>
|
||||
<spirit:displayName>Rs232 Clock Frequency</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.UART_CLOCK_FREQUENCY" spirit:minimum="0" spirit:rangeType="long">100000000</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_M00_AXIS_RX_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M00 Axis Rx Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_S00_AXIS_TX_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axis Tx Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_23c37a81</spirit:name>
|
||||
<spirit:enumeration>2400</spirit:enumeration>
|
||||
<spirit:enumeration>4800</spirit:enumeration>
|
||||
<spirit:enumeration>9600</spirit:enumeration>
|
||||
<spirit:enumeration>19200</spirit:enumeration>
|
||||
<spirit:enumeration>38400</spirit:enumeration>
|
||||
<spirit:enumeration>57600</spirit:enumeration>
|
||||
<spirit:enumeration>115200</spirit:enumeration>
|
||||
<spirit:enumeration>230400</spirit:enumeration>
|
||||
<spirit:enumeration>460800</spirit:enumeration>
|
||||
<spirit:enumeration>921600</spirit:enumeration>
|
||||
<spirit:enumeration>1000000</spirit:enumeration>
|
||||
<spirit:enumeration>1500000</spirit:enumeration>
|
||||
<spirit:enumeration>2000000</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_6fc15197</spirit:name>
|
||||
<spirit:enumeration>32</spirit:enumeration>
|
||||
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|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_9d8b0d81</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_d8920bdd</spirit:name>
|
||||
<spirit:enumeration>8</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
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|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
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|
||||
<spirit:file>
|
||||
<spirit:name>hdl/UART_Engine.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/UART_Manager.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>hdl/AXI4Stream_UART_v1_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_dad462a3</spirit:userFileType>
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<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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||||
<spirit:name>hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
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|
||||
<spirit:file>
|
||||
<spirit:name>hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
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|
||||
<spirit:file>
|
||||
<spirit:name>hdl/UART_Engine.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
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|
||||
<spirit:file>
|
||||
<spirit:name>hdl/UART_Manager.vhd</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
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|
||||
<spirit:file>
|
||||
<spirit:name>hdl/AXI4Stream_UART_v1_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
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||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>xgui/AXI4Stream_UART_v1_1.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
|
||||
<spirit:userFileType>CHECKSUM_5514ca69</spirit:userFileType>
|
||||
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
||||
</spirit:file>
|
||||
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|
||||
<spirit:fileSet>
|
||||
<spirit:name>bd_tcl_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>bd/bd.tcl</spirit:name>
|
||||
<spirit:fileType>tclSource</spirit:fileType>
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||||
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||||
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||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
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||||
<spirit:file>
|
||||
<spirit:name>utils/board/board.xit</spirit:name>
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||||
<spirit:userFileType>xit</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">AXI4Stream_UART_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>UART_BAUD_RATE</spirit:name>
|
||||
<spirit:displayName>Baud Rate</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BAUD_RATE" spirit:choiceRef="choice_list_23c37a81">115200</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>UART_CLOCK_FREQUENCY</spirit:name>
|
||||
<spirit:displayName>Rs232 Clock Frequency</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_CLOCK_FREQUENCY">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_M00_AXIS_RX_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M00 Axis Rx Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd">8</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_M00_AXIS_RX_TDATA_WIDTH">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_S00_AXIS_TX_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axis Tx Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1000">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>UART_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:order="1001">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
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||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
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||||
<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/AXI_Peripheral</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>AXI4-Stream UART</xilinx:displayName>
|
||||
<xilinx:xpmLibraries>
|
||||
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
||||
</xilinx:xpmLibraries>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:upgrades>
|
||||
<xilinx:canUpgradeFrom>TimeEngineers:ip:AXI4Stream_UART:1.0</xilinx:canUpgradeFrom>
|
||||
</xilinx:upgrades>
|
||||
<xilinx:coreCreationDateTime>2021-01-15T12:00:01Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b59b4e5a"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="adabba16"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="a9681487"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f305a3bd"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="06447ef8"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
Reference in New Issue
Block a user