Add AXI4-Stream UART IP and associated files
- Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.
This commit is contained in:
343
LAB3/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd
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343
LAB3/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:02:15 01/23/2016
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-- Design Name:
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-- Module Name: uart - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- UART
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-- Implements a universal asynchronous receiver transmitter
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-------------------------------------------------------------------------------
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-- clock
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-- Input clock, must match frequency value given on clock_frequency
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-- generic input.
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-- reset
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-- Synchronous reset.
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-- data_stream_in
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-- Input data bus for bytes to transmit.
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-- data_stream_in_stb
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-- Input strobe to qualify the input data bus.
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-- data_stream_in_ack
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-- Output acknowledge to indicate the UART has begun sending the byte
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-- provided on the data_stream_in port.
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-- data_stream_in_done
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-- Output pulse che arriva quando fine tx
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-- data_stream_out
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-- Data output port for received bytes.
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-- data_stream_out_stb
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-- Output strobe to qualify the received byte. Will be valid for one clock
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-- cycle only.
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-- tx
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-- Serial transmit.
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-- rx
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-- Serial receive
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity UART_Engine is
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generic (
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BAUD_RATE : integer range 110 to 2000000;
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CLOCK_FREQUENCY : positive
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);
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port (
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clock : in std_logic;
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reset : in std_logic;
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data_stream_in : in std_logic_vector(7 downto 0);
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data_stream_in_stb : in std_logic;
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data_stream_in_ack : out std_logic;
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data_stream_in_done : out std_logic;
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data_stream_out : out std_logic_vector(7 downto 0);
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data_stream_out_stb : out std_logic;
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tx : out std_logic;
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rx : in std_logic
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);
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end UART_Engine;
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architecture rtl of UART_Engine is
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---------------------------------------------------------------------------
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-- Baud generation constants
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---------------------------------------------------------------------------
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constant c_tx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE)));
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constant c_rx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16)));
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---------------------------------------------------------------------------
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-- Baud generation signals
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---------------------------------------------------------------------------
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signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0;
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signal tx_baud_tick : std_logic := '0';
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signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0;
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signal rx_baud_tick : std_logic := '0';
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---------------------------------------------------------------------------
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-- Transmitter signals
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---------------------------------------------------------------------------
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type uart_tx_states is (
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tx_send_start_bit,
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tx_send_data,
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tx_send_stop_bit
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);
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signal uart_tx_state : uart_tx_states := tx_send_start_bit;
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signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
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signal uart_tx_data : std_logic := '1';
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signal uart_tx_count : unsigned(2 downto 0) := (others => '0');
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signal uart_rx_data_in_ack : std_logic := '0';
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signal uart_rx_data_in_done : std_logic := '0';
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---------------------------------------------------------------------------
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-- Receiver signals
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---------------------------------------------------------------------------
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type uart_rx_states is (
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rx_get_start_bit,
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rx_get_data,
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rx_get_stop_bit
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);
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signal uart_rx_state : uart_rx_states := rx_get_start_bit;
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signal uart_rx_bit : std_logic := '1';
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signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
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signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1');
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signal uart_rx_filter : unsigned(1 downto 0) := (others => '1');
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signal uart_rx_count : unsigned(2 downto 0) := (others => '0');
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signal uart_rx_data_out_stb : std_logic := '0';
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signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
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signal uart_rx_bit_tick : std_logic := '0';
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begin
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-- Connect IO
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data_stream_in_ack <= uart_rx_data_in_ack;
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data_stream_in_done <= uart_rx_data_in_done;
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data_stream_out <= uart_rx_data_vec;
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data_stream_out_stb <= uart_rx_data_out_stb;
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tx <= uart_tx_data;
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---------------------------------------------------------------------------
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-- OVERSAMPLE_CLOCK_DIVIDER
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-- generate an oversampled tick (baud * 16)
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---------------------------------------------------------------------------
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oversample_clock_divider : process (clock)
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begin
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if rising_edge (clock) then
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if reset = '1' then
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rx_baud_counter <= 0;
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rx_baud_tick <= '0';
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else
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if rx_baud_counter = c_rx_div - 1 then
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rx_baud_counter <= 0;
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rx_baud_tick <= '1';
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else
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rx_baud_counter <= rx_baud_counter + 1;
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rx_baud_tick <= '0';
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end if;
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end if;
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end if;
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end process oversample_clock_divider;
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---------------------------------------------------------------------------
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-- RXD_SYNCHRONISE
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-- Synchronise rxd to the oversampled baud
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---------------------------------------------------------------------------
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rxd_synchronise : process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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uart_rx_data_sr <= (others => '1');
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else
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if rx_baud_tick = '1' then
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uart_rx_data_sr(0) <= rx;
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uart_rx_data_sr(1) <= uart_rx_data_sr(0);
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end if;
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end if;
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end if;
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end process rxd_synchronise;
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---------------------------------------------------------------------------
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-- RXD_FILTER
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-- Filter rxd with a 2 bit counter.
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---------------------------------------------------------------------------
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rxd_filter : process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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uart_rx_filter <= (others => '1');
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uart_rx_bit <= '1';
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else
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if rx_baud_tick = '1' then
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-- filter rxd.
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if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then
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uart_rx_filter <= uart_rx_filter + 1;
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elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
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uart_rx_filter <= uart_rx_filter - 1;
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end if;
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-- set the rx bit.
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if uart_rx_filter = 3 then
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uart_rx_bit <= '1';
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elsif uart_rx_filter = 0 then
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uart_rx_bit <= '0';
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end if;
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end if;
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end if;
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end if;
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end process rxd_filter;
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---------------------------------------------------------------------------
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-- RX_BIT_SPACING
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---------------------------------------------------------------------------
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rx_bit_spacing : process (clock)
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begin
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if rising_edge(clock) then
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uart_rx_bit_tick <= '0';
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if rx_baud_tick = '1' then
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if uart_rx_bit_spacing = 15 then
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uart_rx_bit_tick <= '1';
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uart_rx_bit_spacing <= (others => '0');
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else
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uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
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end if;
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if uart_rx_state = rx_get_start_bit then
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uart_rx_bit_spacing <= (others => '0');
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end if;
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end if;
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end if;
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end process rx_bit_spacing;
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---------------------------------------------------------------------------
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-- UART_RECEIVE_DATA
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---------------------------------------------------------------------------
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uart_receive_data : process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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uart_rx_state <= rx_get_start_bit;
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uart_rx_data_vec <= (others => '0');
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uart_rx_count <= (others => '0');
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uart_rx_data_out_stb <= '0';
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else
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uart_rx_data_out_stb <= '0';
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case uart_rx_state is
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when rx_get_start_bit =>
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if rx_baud_tick = '1' and uart_rx_bit = '0' then
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uart_rx_state <= rx_get_data;
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end if;
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when rx_get_data =>
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if uart_rx_bit_tick = '1' then
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uart_rx_data_vec(uart_rx_data_vec'high)
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<= uart_rx_bit;
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uart_rx_data_vec(
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uart_rx_data_vec'high-1 downto 0
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) <= uart_rx_data_vec(
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uart_rx_data_vec'high downto 1
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);
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if uart_rx_count < 7 then
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uart_rx_count <= uart_rx_count + 1;
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else
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uart_rx_count <= (others => '0');
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uart_rx_state <= rx_get_stop_bit;
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end if;
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end if;
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when rx_get_stop_bit =>
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if uart_rx_bit_tick = '1' then
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if uart_rx_bit = '1' then
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uart_rx_state <= rx_get_start_bit;
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uart_rx_data_out_stb <= '1';
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end if;
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end if;
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when others =>
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uart_rx_state <= rx_get_start_bit;
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end case;
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end if;
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end if;
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end process uart_receive_data;
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---------------------------------------------------------------------------
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-- TX_CLOCK_DIVIDER
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-- Generate baud ticks at the required rate based on the input clock
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-- frequency and baud rate
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---------------------------------------------------------------------------
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tx_clock_divider : process (clock)
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begin
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if rising_edge (clock) then
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if reset = '1' then
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tx_baud_counter <= 0;
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tx_baud_tick <= '0';
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else
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if tx_baud_counter = c_tx_div - 1 then
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tx_baud_counter <= 0;
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tx_baud_tick <= '1';
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else
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tx_baud_counter <= tx_baud_counter + 1;
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tx_baud_tick <= '0';
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end if;
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end if;
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end if;
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end process tx_clock_divider;
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---------------------------------------------------------------------------
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-- UART_SEND_DATA
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-- Get data from data_stream_in and send it one bit at a time upon each
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-- baud tick. Send data lsb first.
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-- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1)
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---------------------------------------------------------------------------
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uart_send_data : process(clock)
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begin
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if rising_edge(clock) then
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if reset = '1' then
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uart_tx_data <= '1';
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uart_tx_data_vec <= (others => '0');
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uart_tx_count <= (others => '0');
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uart_tx_state <= tx_send_start_bit;
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uart_rx_data_in_ack <= '0';
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uart_rx_data_in_done <= '0';
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else
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uart_rx_data_in_ack <= '0';
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uart_rx_data_in_done <= '0'; --new
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case uart_tx_state is
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when tx_send_start_bit =>
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if tx_baud_tick = '1' and data_stream_in_stb = '1' then
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uart_tx_data <= '0';
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uart_tx_state <= tx_send_data;
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uart_tx_count <= (others => '0');
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uart_rx_data_in_ack <= '1';
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uart_tx_data_vec <= data_stream_in;
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end if;
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when tx_send_data =>
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if tx_baud_tick = '1' then
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uart_tx_data <= uart_tx_data_vec(0);
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uart_tx_data_vec(
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uart_tx_data_vec'high-1 downto 0
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) <= uart_tx_data_vec(
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uart_tx_data_vec'high downto 1
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);
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if uart_tx_count < 7 then
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uart_tx_count <= uart_tx_count + 1;
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else
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uart_tx_count <= (others => '0');
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uart_tx_state <= tx_send_stop_bit;
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end if;
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end if;
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when tx_send_stop_bit =>
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if tx_baud_tick = '1' then
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uart_tx_data <= '1';
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uart_tx_state <= tx_send_start_bit;
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uart_rx_data_in_done <= '1'; --new
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end if;
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when others =>
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uart_tx_data <= '1';
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uart_tx_state <= tx_send_start_bit;
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end case;
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end if;
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end if;
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end process uart_send_data;
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end rtl;
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