Add AXI4-Stream UART IP and associated files

- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.

LAB3/ip/AXI4-Stream_UART/utils/board/board.xit

@@ -0,0 +1,17 @@
+package require xilinx::board 1.0
+namespace import ::xilinx::board::*
+
+set instname [current_inst]
+set f_xdc [add_ipfile -usedIn  [list synthesis implementation board ] -force ${instname}_board.xdc]
+puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n"
+if { [get_project_property BOARD] == "" } {
+    close_ipfile $f_xdc
+    return
+}
+
+set board_if [get_property PARAM_VALUE.UART_BOARD_INTERFACE]
+if { $board_if ne "Custom"} {
+	board_add_port_constraints $f_xdc $board_if TxD UART_TX
+	board_add_port_constraints $f_xdc $board_if RxD UART_RX
+}
+close_ipfile $f_xdc