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Add AXI4-Stream UART IP and associated files

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- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.
This commit is contained in:
Davide Cavagnola
2025-05-12 18:16:58 +02:00
parent a4ec7ce43a
commit b11c65043f
20 changed files with 3906 additions and 6 deletions
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36
LAB3/ip/AXI4-Stream_UART/vv_index.xml Normal file
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<?xml version="1.0"?>
<Index Version="1" Minor="0">
<Repository value="/home/nicola/Documents/vivado/axi4-stream-uart">
</Repository>
<IP>
<VLNV value="xilinx.com:user:AXI4Stream_UART:1.0">
</VLNV>
<DisplayName value="AXI4-Stream UART">
</DisplayName>
<Description value="AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output">
</Description>
<CoreRevision value="8">
</CoreRevision>
<ComponentPath value="component.xml">
</ComponentPath>
<Families>
<Family name="artix7">
<Part status="Production" name="ALL">
</Part>
</Family>
<Family name="zynq">
<Part status="Production" name="ALL">
</Part>
</Family>
</Families>
<Taxonomies>
<Taxonomy value="AXI_Peripheral">
</Taxonomy>
</Taxonomies>
<Interfaces>
<Interface value="AXI4-Stream">
</Interface>
</Interfaces>
</IP>
</Index>