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Add AXI4-Stream UART IP and associated files

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- Created board.xit for physical constraints related to UART interface.
- Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata.
- Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl.
- Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings.
- Configured file sets and simulation options for both projects.
This commit is contained in:
Davide Cavagnola
2025-05-12 18:16:58 +02:00
parent a4ec7ce43a
commit b11c65043f
20 changed files with 3906 additions and 6 deletions
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85
LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Settings [ipgui::add_page $IPINST -name "Settings"]
ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox
}
proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to validate UART_BAUD_RATE
return true
}
proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to validate UART_CLOCK_FREQUENCY
return true
}
proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to validate USE_BOARD_FLOW
return true
}
proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to validate UART_BOARD_INTERFACE
return true
}
proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
}
proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY}
}
proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}
}

85
LAB3/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Settings [ipgui::add_page $IPINST -name "Settings"]
ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox
}
proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to validate UART_BAUD_RATE
return true
}
proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to validate UART_CLOCK_FREQUENCY
return true
}
proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to validate USE_BOARD_FLOW
return true
}
proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to validate UART_BOARD_INTERFACE
return true
}
proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
}
proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY}
}
proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}
}