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final commit

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This commit is contained in:
Davide Cavagnola
2025-03-18 00:27:28 +01:00
parent 797b2c0be8
commit b51f25e81b
11 changed files with 1312 additions and 0 deletions
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83
LAB0/lab0_pulse_width_modulator/lab0_pulse_width_modulator.srcs/sources_1/new/lab0_pulse_width_modulator.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2025 15:23:11
-- Design Name:
-- Module Name: PulseWidthModulator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PulseWidthModulator is
Generic(
BIT_LENGTH : INTEGER RANGE 1 to 16 := 8;
T_ON_INIT : POSITIVE := 64;
PERIOD_INIT : POSITIVE := 128;
PWM_INIT : STD_LOGIC := '0'
);
Port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
Ton : IN std_logic_vector(BIT_LENGTH-1 downto 0);
Period : IN std_logic_vector(BIT_LENGTH-1 downto 0);
PWM : OUT std_logic
);
end PulseWidthModulator;
architecture Behavioral of PulseWidthModulator is
signal counter : unsigned(BIT_LENGTH-1 downto 0) := (others => '0');
signal pwm_out : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
pwm_out <= '0'; -- Assicura PWM spento al reset
elsif rising_edge(clk) then
if counter = unsigned(period) then
counter <= (others => '0'); -- Reset counter
else
counter <= counter + 1; -- Incrementa il counter
end if;
-- Accendi il PWM all'inizio di ogni ciclo
if counter = 0 then
pwm_out <= '1';
end if;
-- Spegni il PWM quando il contatore raggiunge Ton
if counter = unsigned(Ton) then
pwm_out <= '0';
end if;
end if;
end process;
PWM <= pwm_out; -- Output PWM
end Behavioral;

56
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/ShiftRegister_v0.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 14:49:43
-- Design Name:
-- Module Name: ShiftRegister_v0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister_v0 is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC);
end ShiftRegister_v0;
architecture Behavioral of ShiftRegister_v0 is
signal sr : std_logic := '0';
begin
process(clk, reset)
begin
if reset = '1' then
sr <= '0';
elsif rising_edge(clk) then
sr <= din;
end if;
end process;
dout <= sr;
end Behavioral;

56
LAB0/lab0_shift_register_v0/lab0_shift_register_v0.srcs/sources_1/new/shift_register_v0_v0.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 14:21:16
-- Design Name:
-- Module Name: shift_register_v0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shift_register_v0 is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC);
end shift_register_v0;
architecture Behavioral of shift_register_v0 is
signal sr : std_logic := '0';
begin
process(clk, reset)
begin
if reset = '1' then
sr <= '0';
elsif rising_edge(clk) then
sr <= din;
end if;
end process;
dout <= sr;
end Behavioral;

62
LAB0/lab0_shift_register_v1/lab0_shift_register_v1.srcs/sources_1/new/ShiftRegister_v1.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 15:06:26
-- Design Name:
-- Module Name: ShiftRegister_v1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister_v1 is
Generic (
SR_DEPTH : POSITIVE := 4;
SR_INIT : STD_LOGIC := '0'
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC;
dout : out STD_LOGIC
);
end ShiftRegister_v1;
architecture Behavioral of ShiftRegister_v1 is
signal sr : STD_LOGIC_VECTOR(SR_DEPTH-1 DOWNTO 0) := (others => '0');
begin
process(clk, reset)
begin
if reset = '1' then
sr <= (others => SR_INIT);
elsif rising_edge(clk) then
sr <= sr(SR_DEPTH-2 DOWNTO 0) & din;
end if;
end process;
dout <= sr(SR_DEPTH-1);
end Behavioral;

65
LAB0/lab0_shift_register_v2/lab0_shift_register_v2.srcs/sources_1/new/ShiftRegister_v2.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.03.2025 15:35:08
-- Design Name:
-- Module Name: ShiftRegister_v2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ShiftRegister_v2 is
Generic (
SR_WIDTH : NATURAL := 8;
SR_DEPTH : POSITIVE := 4;
SR_INIT : STD_LOGIC := '0'
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0);
dout : out STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0)
);
end ShiftRegister_v2;
architecture Behavioral of ShiftRegister_v2 is
type sr_type is array (SR_DEPTH-1 downto 0) of std_logic_vector(SR_WIDTH-1 downto 0);
signal sr : sr_type := (others => (others => SR_INIT));
begin
process(reset,clk)
begin
if reset = '1' then
sr <= (others => (others => SR_INIT));
elsif rising_edge(clk) then
sr <= sr(SR_DEPTH-2 downto 0) & din;
end if;
end process;
dout <= sr(SR_DEPTH-1);
end Behavioral;

255
LAB0/tb_PulseWidthModulator/tb_PulseWidthModulator.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.03.2019 18:55:36
-- Design Name:
-- Module Name: tb_PulseWidthModulator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
---------- DEFAULT LIBRARY ---------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
-- use IEEE.MATH_REAL.all;
-- use STD.textio.all;
-- use ieee.std_logic_textio.all;
------------------------------------
---------- OTHERS LIBRARY ----------
-- NONE
------------------------------------
entity tb_PulseWidthModulator is
end tb_PulseWidthModulator;
architecture Behavioral of tb_PulseWidthModulator is
------------------ CONSTANT DECLARATION -------------------------
--------- Timing -----------
constant CLK_PERIOD : TIME := 10 ns;
constant RESET_WND : TIME := 10*CLK_PERIOD;
constant PWM_WND : TIME := 100 ns;
----------------------------
--- TB Initialiazzations ---
constant TB_CLK_INIT : STD_LOGIC := '0';
constant TB_RESET_INIT : STD_LOGIC := '1';
----------------------------
------- DUT Generics -------
constant DUT_BIT_LENGTH : INTEGER RANGE 1 TO 16 := 3; -- Leds used over the 16 in Basys3
constant DUT_T_ON_INIT : POSITIVE := 8; -- Init of Ton
constant DUT_PERIOD_INIT : POSITIVE := 16; -- Init of Periof
constant DUT_PWM_INIT : STD_LOGIC := '1'; -- Init of PWM
----------------------------
-----------------------------------------------------------------
------ COMPONENT DECLARATION for the Device Under Test (DUT) ------
----------- DUT -----------
component PulseWidthModulator
Generic(
BIT_LENGTH : INTEGER RANGE 1 TO 16; -- Leds used over the 16 in Basys3
T_ON_INIT : POSITIVE; -- Init of Ton
PERIOD_INIT : POSITIVE; -- Init of Periof
PWM_INIT : STD_LOGIC -- Init of PWM
);
Port (
------- Reset/Clock --------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
----------------------------
-------- Duty Cycle ----------
Ton : IN STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0); -- clk at PWM = '1'
Period : IN STD_LOGIC_VECTOR(BIT_LENGTH-1 downto 0); -- clk per period of PWM
PWM : OUT STD_LOGIC -- PWM signal
----------------------------
);
end component;
----------------------------
------------------------------------------------------------------
--------------------- SIGNALS DECLARATION -----------------------
------- Clock/Reset -------
signal reset : STD_LOGIC := TB_RESET_INIT;
signal clk : STD_LOGIC := TB_CLK_INIT;
----------------------------
-------- Duty Cycle ----------
signal dut_Ton : STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0); -- clk at PWM = '1'
signal dut_Period : STD_LOGIC_VECTOR(DUT_BIT_LENGTH-1 downto 0); -- clk per period of PWM
signal dut_PWM : STD_LOGIC; -- PWM signal
----------------------------
----------------------------------------------------------------
begin
--------------------- COMPONENTS DUT WRAPPING --------------------
----------- DUT ------------
dut_PulseWidthModulator : PulseWidthModulator
Generic Map(
BIT_LENGTH => DUT_BIT_LENGTH,
T_ON_INIT => DUT_T_ON_INIT,
PERIOD_INIT => DUT_PERIOD_INIT,
PWM_INIT => DUT_PWM_INIT
)
Port Map(
------- Reset/Clock --------
reset => reset,
clk => clk,
----------------------------
-------- Duty Cycle ----------
Ton => dut_Ton,
Period => dut_Period,
PWM => dut_PWM
----------------------------
);
----------------------------
----------------------------
-------------------------------------------------------------------
--------------------- TEST BENCH DATA FLOW -----------------------
---------- clock ----------
clk <= not clk after CLK_PERIOD/2;
----------------------------
-------------------------------------------------------------------
---------------------- TEST BENCH PROCESS -------------------------
---- Clock Process --------
-- clk_wave :process
-- begin
-- clk <= CLK_PERIOD;
-- wait for CLK_PERIOD/2;
-- clk <= not clk;
-- wait for CLK_PERIOD/2;
-- end process;
--------------------------
----- Reset Process --------
reset_wave :process
begin
reset <= TB_RESET_INIT;
wait for RESET_WND;
reset <= not reset;
wait;
end process;
----------------------------
------ Stimulus process -------
stim_proc: process
begin
-- waiting the reset wave
dut_Ton <= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH));
dut_Period <= std_logic_vector(to_unsigned(0,DUT_BIT_LENGTH));
wait for RESET_WND;
-- Start
for I in 0 to 2**DUT_BIT_LENGTH-1 loop
dut_Period <= std_logic_vector(to_unsigned(I,DUT_BIT_LENGTH));
for J in 0 to 2**DUT_BIT_LENGTH-1 loop
dut_Ton <= std_logic_vector(to_unsigned(J,DUT_BIT_LENGTH));
wait for PWM_WND;
end loop;
end loop;
dut_Ton <= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-1,DUT_BIT_LENGTH));
dut_Period <= std_logic_vector(to_unsigned(2**DUT_BIT_LENGTH-2,DUT_BIT_LENGTH));
wait for PWM_WND;
-- Stop
wait;
--------------------------
wait;
end process;
----------------------------
-------------------------------------------------------------------
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2019 12:46:18
-- Design Name:
-- Module Name: tb_ShiftRegister_v0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ShiftRegister_v0 is
end tb_ShiftRegister_v0;
architecture Behavioral of tb_ShiftRegister_v0 is
------------------------ Constant Declaration -------------------------
-- Constant For Test Bench (TB) --
constant RESET_ON : STD_LOGIC := '1';
constant CLK_PERIOD : time := 10 ns;
constant RESET_WND : time := 100 ns;
----------------------------------
----------------------------------------------------------------------
----------------- Device Under Test (DUT) Declaration ----------------
------------ DUT v0 --------------
COMPONENT ShiftRegister_v0
Port (
---------- Reset/Clock ----------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
---------------------------------
------------- Data --------------
din : IN STD_LOGIC;
dout : OUT STD_LOGIC
---------------------------------
);
END COMPONENT;
----------------------------------
----------------------------------------------------------------------
------------------------- Signal Declaration -------------------------
---------- Reset/Clock ----------
signal reset : STD_LOGIC := RESET_ON;
signal clk : STD_LOGIC := '1';
---------------------------------
-------- ShiftRegister_v0 -------
signal dut0_din : STD_LOGIC := '0';
signal dut0_dout : STD_LOGIC;
---------------------------------
----------------------------------------------------------------------
begin
------------------- Device Under Test (DUT) Wrapper ------------------
------------ DUT v0 --------------
dut0_ShiftRegister_v0 : ShiftRegister_v0
Port Map(
---------- Reset/Clock ----------
reset => reset,
clk => clk,
---------------------------------
------------- Data --------------
din => dut0_din,
dout => dut0_dout
---------------------------------
);
----------------------------------
----------------------------------------------------------------------
-------------------------- Signals Generation -------------------------
------ TB Clk Generation -------
clk <= not clk after CLK_PERIOD/2;
---------------------------------
----- TB Reset Generation ------
reset_wave : process
begin
reset <= '1';
wait for RESET_WND;
reset <= '0';
wait;
end process;
---------------------------------
-- TB din pattern Generation ---
dut0_din_pattern : process
begin
-- wait the reset window
dut0_din <= '0';
wait for RESET_WND;
-- Start
dut0_din <= '0';
wait for CLK_PERIOD;
dut0_din <= '1';
wait for 4*CLK_PERIOD;
dut0_din <= '0';
wait for 8*CLK_PERIOD;
-- Etc...
-- Stop
wait;
end process;
---------------------------------
----------------------------------------------------------------------
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2019 13:27:59
-- Design Name:
-- Module Name: tb_ShiftRegister_v1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ShiftRegister_v1 is
end tb_ShiftRegister_v1;
architecture Behavioral of tb_ShiftRegister_v1 is
------------------------ Constant Declaration -------------------------
-- Constant For Test Bench (TB) --
constant RESET_ON : STD_LOGIC := '1';
constant CLK_PERIOD : time := 10 ns;
constant RESET_WND : time := 100 ns;
----------------------------------
------ Constant For DUT v0 ------
constant DUT1_SR_DEPTH : POSITIVE := 4;
constant DUT1_SR_INIT : STD_LOGIC := '0';
----------------------------------
----------------------------------------------------------------------
----------------- Device Under Test (DUT) Declaration ----------------
------------ DUT v1 --------------
COMPONENT ShiftRegister_v1
Generic(
SR_DEPTH : POSITIVE;
SR_INIT : STD_LOGIC
);
Port (
---------- Reset/Clock ----------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
---------------------------------
------------- Data --------------
din : IN STD_LOGIC;
dout : OUT STD_LOGIC
---------------------------------
);
END COMPONENT;
----------------------------------
----------------------------------------------------------------------
------------------------- Signal Declaration -------------------------
---------- Reset/Clock ----------
signal reset : STD_LOGIC := RESET_ON;
signal clk : STD_LOGIC := '1';
---------------------------------
-------- ShiftRegister_v1 -------
signal dut1_din : STD_LOGIC := '0';
signal dut1_dout : STD_LOGIC;
---------------------------------
----------------------------------------------------------------------
begin
------------------- Device Under Test (DUT) Wrapper ------------------
------------ DUT v1 --------------
dut1_ShiftRegister_v1 : ShiftRegister_v1
Generic Map(
SR_DEPTH => DUT1_SR_DEPTH,
SR_INIT => DUT1_SR_INIT
)
Port Map(
---------- Reset/Clock ----------
reset => reset,
clk => clk,
---------------------------------
------------- Data --------------
din => dut1_din,
dout => dut1_dout
---------------------------------
);
----------------------------------
----------------------------------------------------------------------
-------------------------- Signals Generation -------------------------
------ TB Clk Generation -------
clk <= not clk after CLK_PERIOD/2;
---------------------------------
----- TB Reset Generation ------
reset_wave : process
begin
reset <= '1';
wait for RESET_WND;
reset <= '0';
wait;
end process;
---------------------------------
-- TB din pattern Generation ---
dut1_din_pattern : process
begin
-- wait the reset window
dut1_din <= '0';
wait for RESET_WND;
-- Start
dut1_din <= '0';
wait for CLK_PERIOD;
dut1_din <= '1';
wait for 4*CLK_PERIOD;
dut1_din <= '0';
wait for 8*CLK_PERIOD;
-- Etc...
-- Stop
wait;
end process;
---------------------------------
----------------------------------------------------------------------
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07.03.2019 16:39:28
-- Design Name:
-- Module Name: tb_ShiftRegister_v2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_ShiftRegister_v2 is
end tb_ShiftRegister_v2;
architecture Behavioral of tb_ShiftRegister_v2 is
------------------------ Constant Declaration -------------------------
-- Constant For Test Bench (TB) --
constant RESET_ON : STD_LOGIC := '1';
constant CLK_PERIOD : time := 10 ns;
constant RESET_WND : time := 100 ns;
----------------------------------
------ Constant For DUT v2 ------
constant DUT2_SR_WIDTH : NATURAL := 8;
constant DUT2_SR_DEPTH : POSITIVE := 4;
constant DUT2_SR_INIT : STD_LOGIC := '0';
----------------------------------
----------------------------------------------------------------------
----------------- Device Under Test (DUT) Declaration ----------------
------------ DUT v2 --------------
COMPONENT ShiftRegister_v2
Generic(
SR_WIDTH : NATURAL := 7;
SR_DEPTH : POSITIVE := 4;
SR_INIT : STD_LOGIC := '0'
);
Port (
---------- Reset/Clock ----------
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
---------------------------------
------------- Data --------------
din : IN STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0);
dout : OUT STD_LOGIC_VECTOR(SR_WIDTH-1 downto 0)
---------------------------------
);
END COMPONENT;
----------------------------------
----------------------------------------------------------------------
------------------------- Signal Declaration -------------------------
---------- Reset/Clock ----------
signal reset : STD_LOGIC := RESET_ON;
signal clk : STD_LOGIC := '1';
---------------------------------
-------- ShiftRegister_v2 -------
signal dut2_din : STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0) := (Others => '0');
signal dut2_dout : STD_LOGIC_VECTOR(DUT2_SR_WIDTH-1 downto 0);
---------------------------------
----------------------------------------------------------------------
begin
------------------- Device Under Test (DUT) Wrapper ------------------
------------ DUT v2 --------------
dut2_ShiftRegister_v2 : ShiftRegister_v2
Generic Map(
SR_WIDTH => DUT2_SR_WIDTH,
SR_DEPTH => DUT2_SR_DEPTH,
SR_INIT => DUT2_SR_INIT
)
Port Map(
---------- Reset/Clock ----------
reset => reset,
clk => clk,
---------------------------------
------------- Data --------------
din => dut2_din,
dout => dut2_dout
---------------------------------
);
----------------------------------
----------------------------------------------------------------------
-------------------------- Signals Generation -------------------------
------ TB Clk Generation -------
clk <= not clk after CLK_PERIOD/2;
---------------------------------
----- TB Reset Generation ------
reset_wave : process
begin
reset <= '1';
wait for RESET_WND;
reset <= '0';
wait;
end process;
---------------------------------
-- TB din pattern Generation ---
dut2_din_pattern : process
begin
-- wait the reset window
dut2_din <= (Others => '0');
wait for RESET_WND;
-- Start
dut2_din <= (Others => '0');
wait for CLK_PERIOD;
dut2_din <= (Others => '1');
wait for 4*CLK_PERIOD;
dut2_din <= (Others => '0');
wait for 8*CLK_PERIOD;
-- Etc...
-- Stop
wait;
end process;
---------------------------------
----------------------------------------------------------------------
end Behavioral;