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README.md

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-# VHDL Laboratory – Digital Electronic System Design  
+# Digital Electronic System Design  
-Politecnico di Milano (2024-2025)  
+**Politecnico di Milano (2024-2025)**  
 
-## Overview  
+## 📖 Overview  
-This repository contains VHDL projects and exercises from the **Digital Electronic System Design Laboratory** at **Politecnico di Milano** (Course Code: 054083). The course focuses on **FPGA-based digital design** using VHDL, simulation, synthesis, and implementation.  
+Welcome to the **Digital Electronic System Design Laboratory** repository!  
+This repository contains VHDL projects and exercises from the course **Digital Electronic System Design** at **Politecnico di Milano** *(Course Code: 054083)*.  
 
-## Tools & Hardware  
+The course focuses on:  
-- **Software**: Xilinx Vivado 2020.2 (WebPack Edition)  
+- **FPGA-based digital design**  
-- **Hardware**: Digilent Basys 3 (Xilinx Artix-7 FPGA - *XC7A35T-1CPG236C*)
+- **VHDL simulation, synthesis, and implementation**  
 
-## Course Goals  
+## 🛠️ Tools & Hardware  
-- Develop practical skills for FPGA-based digital system design  
+- **Software**:  
-- Implement and test VHDL architectures using Vivado and Basys 3  
+  - [Xilinx Vivado 2020.2](https://www.xilinx.com/products/design-tools/vivado.html) *(WebPack Edition)*  
-- Learn FPGA timing, power, I/O, and memory management
+- **Hardware**:  
+  - [Digilent Basys 3](https://digilent.com/shop/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/)  
+    - FPGA: *Xilinx Artix-7* (**XC7A35TCPG236C-1**)  
+
+## 🎯 Course Goals  
+- Develop practical skills for **FPGA-based digital system design**  
+- Implement and test **VHDL architectures** using Vivado and Basys 3  
+- Learn about **FPGA timing, power, I/O, and memory management**  
+
+<!-- ## 📂 Repository Structure  
+This section outlines the organization of the repository, including directories for source files, simulations, and documentation. -->
+
+## 📬 Contact  
+For any questions or issues open an issue in this repository.