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Update design files for LAB3: reorganize components and adjust simulation settings

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This commit is contained in:
Davide Cavagnola
2025-05-12 14:38:11 +02:00
parent 60a8aa912d
commit c99622188d
8 changed files with 142 additions and 157 deletions
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1
.gitignore vendored
View File

@@ -75,6 +75,7 @@ vivado*.backup.log
**/design/**/synth/
**/design/**/ui/
**/design/**/hw_handoff/
**/design/**/*.xdc
# Other files
**/test/*.zip

4
LAB2/design/lab_2/hdl/lab_2_wrapper.vhd
View File

@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 22:08:38 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Date : Mon May 12 14:33:04 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper
--Purpose : IP block netlist

16
LAB2/design/lab_2/lab_2.bd
View File

@@ -1176,11 +1176,11 @@
"system_ila_0/SLOT_2_AXIS"
]
},
"img_conv_0_m_axis": {
"Conn": {
"interface_ports": [
"img_conv_0/m_axis",
"packetizer_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
]
},
"AXI4Stream_UART_0_UART": {
@@ -1201,11 +1201,11 @@
"AXI4Stream_UART_0/S00_AXIS_TX"
]
},
"Conn": {
"img_conv_0_m_axis": {
"interface_ports": [
"rgb2gray_0/s_axis",
"depacketizer_0/m_axis",
"system_ila_0/SLOT_0_AXIS"
"img_conv_0/m_axis",
"packetizer_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
}
},

12
LAB2/design/lab_2/lab_2.bda
View File

@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
<data key="VM">lab_2</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VM">lab_2</data>
<data key="VT">VR</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n2">
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n2" target="n0">
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>

20
LAB2/vivado/lab2/lab2.xpr
View File

@@ -55,13 +55,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="6"/>
<Option Name="WTModelSimExportSim" Val="6"/>
<Option Name="WTQuestaExportSim" Val="6"/>
<Option Name="WTIesExportSim" Val="6"/>
<Option Name="WTVcsExportSim" Val="6"/>
<Option Name="WTRivieraExportSim" Val="6"/>
<Option Name="WTActivehdlExportSim" Val="6"/>
<Option Name="WTXSimExportSim" Val="7"/>
<Option Name="WTModelSimExportSim" Val="7"/>
<Option Name="WTQuestaExportSim" Val="7"/>
<Option Name="WTIesExportSim" Val="7"/>
<Option Name="WTVcsExportSim" Val="7"/>
<Option Name="WTRivieraExportSim" Val="7"/>
<Option Name="WTActivehdlExportSim" Val="7"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -203,17 +203,16 @@
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/synth_1">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
@@ -226,7 +225,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>

62
LAB3/design/lab_3/lab_3.bd
View File

@@ -13,9 +13,7 @@
"design_tree": {
"clk_wiz_0": "",
"proc_sys_reset_0": "",
"axis_dual_i2s_0": "",
"proc_sys_reset_1": "",
"axi4stream_spi_master_0": "",
"digilent_jstk2_0": "",
"edge_detector_toggle_0": "",
"edge_detector_toggle_1": "",
@@ -28,7 +26,9 @@
"effect_selector_0": "",
"led_controller_0": "",
"led_level_controller_0": "",
"mute_controller_0": ""
"mute_controller_0": "",
"axi4stream_spi_master_0": "",
"axis_dual_i2s_0": ""
},
"interface_ports": {
"SPI_M_0": {
@@ -173,32 +173,12 @@
"xci_path": "ip\\lab_3_proc_sys_reset_0_0\\lab_3_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0"
},
"axis_dual_i2s_0": {
"vlnv": "DigiLAB:ip:axis_dual_i2s:1.0",
"xci_name": "lab_3_axis_dual_i2s_0_0",
"xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci",
"inst_hier_path": "axis_dual_i2s_0"
},
"proc_sys_reset_1": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "lab_3_proc_sys_reset_1_0",
"xci_path": "ip\\lab_3_proc_sys_reset_1_0\\lab_3_proc_sys_reset_1_0.xci",
"inst_hier_path": "proc_sys_reset_1"
},
"axi4stream_spi_master_0": {
"vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
"xci_name": "lab_3_axi4stream_spi_master_0_0",
"xci_path": "ip\\lab_3_axi4stream_spi_master_0_0\\lab_3_axi4stream_spi_master_0_0.xci",
"inst_hier_path": "axi4stream_spi_master_0",
"parameters": {
"c_clkfreq": {
"value": "215000000"
},
"c_sclkfreq": {
"value": "5000"
}
}
},
"digilent_jstk2_0": {
"vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
"xci_name": "lab_3_digilent_jstk2_0_0",
@@ -1804,6 +1784,26 @@
"direction": "I"
}
}
},
"axi4stream_spi_master_0": {
"vlnv": "DigiLAB:ip:axi4stream_spi_master:1.0",
"xci_name": "lab_3_axi4stream_spi_master_0_0",
"xci_path": "ip\\lab_3_axi4stream_spi_master_0_0\\lab_3_axi4stream_spi_master_0_0.xci",
"inst_hier_path": "axi4stream_spi_master_0",
"parameters": {
"c_clkfreq": {
"value": "215000000"
},
"c_sclkfreq": {
"value": "5000"
}
}
},
"axis_dual_i2s_0": {
"vlnv": "DigiLAB:ip:axis_dual_i2s:1.0",
"xci_name": "lab_3_axis_dual_i2s_0_0",
"xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci",
"inst_hier_path": "axis_dual_i2s_0"
}
},
"interface_nets": {
@@ -1885,8 +1885,6 @@
"ports": [
"clk_wiz_0/clk_out1",
"proc_sys_reset_0/slowest_sync_clk",
"axis_dual_i2s_0/aclk",
"axi4stream_spi_master_0/aclk",
"digilent_jstk2_0/aclk",
"edge_detector_toggle_0/clk",
"edge_detector_toggle_1/clk",
@@ -1898,7 +1896,9 @@
"balance_controller_0/aclk",
"effect_selector_0/aclk",
"led_level_controller_0/aclk",
"mute_controller_0/aclk"
"mute_controller_0/aclk",
"axi4stream_spi_master_0/aclk",
"axis_dual_i2s_0/aclk"
]
},
"reset_1": {
@@ -1919,15 +1919,13 @@
"clk_wiz_0_clk_out2": {
"ports": [
"clk_wiz_0/clk_out2",
"axis_dual_i2s_0/i2s_clk",
"proc_sys_reset_1/slowest_sync_clk"
"proc_sys_reset_1/slowest_sync_clk",
"axis_dual_i2s_0/i2s_clk"
]
},
"proc_sys_reset_0_peripheral_aresetn": {
"ports": [
"proc_sys_reset_0/peripheral_aresetn",
"axis_dual_i2s_0/aresetn",
"axi4stream_spi_master_0/aresetn",
"digilent_jstk2_0/aresetn",
"debouncer_0/reset",
"axis_broadcaster_0/aresetn",
@@ -1937,7 +1935,9 @@
"balance_controller_0/aresetn",
"effect_selector_0/aresetn",
"led_level_controller_0/aresetn",
"mute_controller_0/aresetn"
"mute_controller_0/aresetn",
"axi4stream_spi_master_0/aresetn",
"axis_dual_i2s_0/aresetn"
]
},
"proc_sys_reset_1_peripheral_aresetn": {

12
LAB3/design/lab_3/lab_3.bda
View File

@@ -26,17 +26,17 @@
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
<node id="n2">
<data key="VM">lab_3</data>
<data key="VT">BC</data>
</node>
<edge id="e0" source="n2" target="n0">
</edge>
<edge id="e1" source="n0" target="n2">
<edge id="e1" source="n0" target="n1">
</edge>
</graph>
</graphml>

172
LAB3/vivado/lab3/lab3.xpr
View File

@@ -55,13 +55,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="1"/>
<Option Name="WTModelSimExportSim" Val="1"/>
<Option Name="WTQuestaExportSim" Val="1"/>
<Option Name="WTIesExportSim" Val="1"/>
<Option Name="WTVcsExportSim" Val="1"/>
<Option Name="WTRivieraExportSim" Val="1"/>
<Option Name="WTActivehdlExportSim" Val="1"/>
<Option Name="WTXSimExportSim" Val="2"/>
<Option Name="WTModelSimExportSim" Val="2"/>
<Option Name="WTQuestaExportSim" Val="2"/>
<Option Name="WTIesExportSim" Val="2"/>
<Option Name="WTVcsExportSim" Val="2"/>
<Option Name="WTRivieraExportSim" Val="2"/>
<Option Name="WTActivehdlExportSim" Val="2"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
@@ -77,48 +77,86 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/LFO.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/balance_controller.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/debouncer.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/digilent_jstk2.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/edge_detector_toggle.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/debouncer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/moving_average_filter_en.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/volume_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/LFO.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/balance_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/effect_selector.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_level_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/mute_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../design/lab_3/lab_3.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../../../lab3.gen/sources_1/bd/lab_3/hdl/lab_3_wrapper.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/all_pass_filter.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
@@ -132,20 +170,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_controller.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_level_controller.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/moving_average_filter.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@@ -153,27 +177,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/moving_average_filter_en.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/mute_controller.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/volume_controller.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/volume_multiplier.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
@@ -188,21 +191,9 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../design/lab_3/lab_3.bd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="LFO"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopArchitecture" Val="Behavioral"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/LFO.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TopModule" Val="lab_3_wrapper"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -218,12 +209,11 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="LFO"/>
<Option Name="TopModule" Val="lab_3_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopArchitecture" Val="Behavioral"/>
<Option Name="TopRTLFile" Val="$PPRDIR/../../src/LFO.vhd"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
@@ -263,9 +253,7 @@
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
@@ -274,9 +262,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>