PickleRick/DESD
1
0
Fork 0
Code Issues 2 Pull Requests Releases Activity

Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

Browse Source
This commit is contained in:
Davide Cavagnola
2025-05-17 16:16:44 +02:00
parent 1eb2181d1d
commit cb57866a2e
5 changed files with 316 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
LAB3/design/diligent_jstk/diligent_jstk.bd
View File

@@ -591,31 +591,24 @@
}
},
"interface_nets": {
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"axi4stream_spi_master_0_SPI_M": {
"interface_ports": [
"SPI_M_0",
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"jstk_uart_bridge_0/s_axis"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS",
"system_ila_0/SLOT_0_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
@@ -628,6 +621,13 @@
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"digilent_jstk2_0_m_axis": {
"interface_ports": [
"digilent_jstk2_0/m_axis",
"axi4stream_spi_master_0/S_AXIS",
"system_ila_0/SLOT_0_AXIS"
]
}
},
"nets": {