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Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

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Davide Cavagnola
2025-05-17 16:16:44 +02:00
parent 1eb2181d1d
commit cb57866a2e
5 changed files with 316 additions and 20 deletions
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LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
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@@ -1,7 +1,7 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Sat May 17 13:12:32 2025
--Date : Sat May 17 14:20:44 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper