PickleRick/DESD
1
0 Fork 0
Code Issues 2 Pull Requests Releases Activity

Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

Browse Source
This commit is contained in:
PickleRick committed 2025-05-17 16:16:44 +02:00
1 parent 1eb2181d1d
commit cb57866a2e
5 files changed
+316 -20
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

LAB3/src/digilent_jstk2.vhd
-1
View File
@@ -81,7 +81,6 @@ BEGIN
IF aresetn = '0' THEN
tx_state <= DELAY;
m_axis_tdata <= (OTHERS => '0');
tx_delay_counter <= 0;
ELSE