Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.

2025-05-17 16:16:44 +02:00
parent 1eb2181d1d
commit cb57866a2e
5 changed files with 316 additions and 20 deletions
--- a/LAB3/src/digilent_jstk2.vhd
+++ b/LAB3/src/digilent_jstk2.vhd
@@ -81,7 +81,6 @@ BEGIN
 			IF aresetn = '0' THEN

 				tx_state <= DELAY;
-				m_axis_tdata <= (OTHERS => '0');
 				tx_delay_counter <= 0;

 			ELSE