Add new AXI4-Stream UART IP and update .gitignore for Lab2 files
This commit is contained in:
13
.gitignore
vendored
13
.gitignore
vendored
@@ -19,8 +19,6 @@
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*.tsi
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*.vcd
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*.vdi
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*.xml
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*.tcl
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*.ltx
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*.xci
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*.dcp
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@@ -44,12 +42,15 @@
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*.qws
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*.wdf
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*.lpr
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*.xdc
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*.bxml
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# Vivado project directories
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*.sim/
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*.cache/
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*.hw/
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*.gen/
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*.srcs/
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.hwdbg/
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*.ip_user_files/
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@@ -68,3 +69,11 @@ vivado*.backup.log
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# SDK workspace
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.sdk/
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# Lab2 files
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LAB2/src/lab_2/ipshared/
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LAB2/src/lab_2/ip/
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LAB2/src/lab_2/sim/
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LAB2/src/lab_2/synth/
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LAB2/src/lab_2/ui/
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LAB2/src/lab_2/hw_handoff/
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89
LAB2/ip/AXI4-Stream_UART/bd/bd.tcl
Normal file
89
LAB2/ip/AXI4-Stream_UART/bd/bd.tcl
Normal file
@@ -0,0 +1,89 @@
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proc init { cellpath otherInfo } {
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set cell_handle [get_bd_cells $cellpath]
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set all_busif [get_bd_intf_pins $cellpath/*]
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set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
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set full_sbusif_list [list ]
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foreach busif $all_busif {
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if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
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set busif_param_list [list]
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set busif_name [get_property NAME $busif]
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if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
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continue
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}
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foreach tparam $axi_standard_param_list {
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lappend busif_param_list "C_${busif_name}_${tparam}"
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}
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bd::mark_propagate_only $cell_handle $busif_param_list
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}
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}
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}
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proc pre_propagate {cellpath otherInfo } {
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set cell_handle [get_bd_cells $cellpath]
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set all_busif [get_bd_intf_pins $cellpath/*]
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set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
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foreach busif $all_busif {
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if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
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continue
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}
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if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
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continue
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}
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set busif_name [get_property NAME $busif]
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foreach tparam $axi_standard_param_list {
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set busif_param_name "C_${busif_name}_${tparam}"
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set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
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set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
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if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
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if { $val_on_cell != "" } {
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set_property CONFIG.${tparam} $val_on_cell $busif
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}
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}
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}
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}
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}
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proc propagate {cellpath otherInfo } {
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set cell_handle [get_bd_cells $cellpath]
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set all_busif [get_bd_intf_pins $cellpath/*]
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set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
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# Set module clock frequency reference to be equal to the input clock.
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set_property CONFIG.UART_CLOCK_FREQUENCY [format %d [get_property CONFIG.FREQ_HZ [get_bd_pins $cellpath/clk_uart]]] $cell_handle
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foreach busif $all_busif {
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if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
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continue
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}
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if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
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continue
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}
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set busif_name [get_property NAME $busif]
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foreach tparam $axi_standard_param_list {
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set busif_param_name "C_${busif_name}_${tparam}"
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set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
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set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
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if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
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#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
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if { $val_on_cell_intf_pin != "" } {
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set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
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}
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}
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}
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}
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}
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765
LAB2/ip/AXI4-Stream_UART/component.xml
Normal file
765
LAB2/ip/AXI4-Stream_UART/component.xml
Normal file
@@ -0,0 +1,765 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>DigiLAB</spirit:vendor>
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<spirit:library>ip</spirit:library>
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<spirit:name>AXI4Stream_UART</spirit:name>
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<spirit:version>1.1</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>M00_AXIS_RX</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_tdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_tvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_tready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>S00_AXIS_TX</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TDATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_tdata</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TVALID</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_tvalid</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>TREADY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>s00_axis_tx_tready</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>WIZ_DATA_WIDTH</spirit:name>
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<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>M00_AXIS_RX_RST</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_aresetn</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>M00_AXIS_RX_CLK</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>CLK</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>m00_axis_rx_aclk</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX_CLK.ASSOCIATED_BUSIF">M00_AXIS_RX</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_RESET</spirit:name>
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<spirit:value spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX_CLK.ASSOCIATED_RESET">m00_axis_rx_aresetn</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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||||
<spirit:busInterface>
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<spirit:name>S00_AXIS_TX_RST</spirit:name>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axis_tx_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX_RST.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>S00_AXIS_TX_CLK</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s00_axis_tx_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX_CLK.ASSOCIATED_BUSIF">S00_AXIS_TX</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX_CLK.ASSOCIATED_RESET">s00_axis_tx_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>reset</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>rst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ClockUART</spirit:name>
|
||||
<spirit:description>Clock used to calculate the delay for UART</spirit:description>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk_uart</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCKUART.ASSOCIATED_BUSIF">UART</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCKUART.ASSOCIATED_RESET">rst</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>UART</spirit:name>
|
||||
<spirit:displayName>UART</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="uart_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>TxD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>UART_TX</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RxD</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>UART_RX</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.UART.BOARD.ASSOCIATED_PARAM">UART_BOARD_INTERFACE</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:presence>required</xilinx:presence>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>vhdl</spirit:language>
|
||||
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|
||||
<spirit:file>
|
||||
<spirit:name>utils/board/board.xit</spirit:name>
|
||||
<spirit:userFileType>xit</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">AXI4Stream_UART_v1_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>UART_BAUD_RATE</spirit:name>
|
||||
<spirit:displayName>Baud Rate</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BAUD_RATE" spirit:choiceRef="choice_list_23c37a81">115200</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>UART_CLOCK_FREQUENCY</spirit:name>
|
||||
<spirit:displayName>Rs232 Clock Frequency</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_CLOCK_FREQUENCY">100000000</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_M00_AXIS_RX_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C M00 Axis Rx Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd">8</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_M00_AXIS_RX_TDATA_WIDTH">false</xilinx:isEnabled>
|
||||
</xilinx:enablement>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_S00_AXIS_TX_TDATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>C S00 Axis Tx Tdata Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1000">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>UART_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:order="1001">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:supportedFamilies>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
|
||||
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
|
||||
</xilinx:supportedFamilies>
|
||||
<xilinx:taxonomies>
|
||||
<xilinx:taxonomy>/AXI_Peripheral</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>AXI4-Stream UART</xilinx:displayName>
|
||||
<xilinx:xpmLibraries>
|
||||
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
|
||||
</xilinx:xpmLibraries>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:upgrades>
|
||||
<xilinx:canUpgradeFrom>TimeEngineers:ip:AXI4Stream_UART:1.0</xilinx:canUpgradeFrom>
|
||||
</xilinx:upgrades>
|
||||
<xilinx:coreCreationDateTime>2021-01-15T12:00:01Z</xilinx:coreCreationDateTime>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b59b4e5a"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="adabba16"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="a9681487"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f305a3bd"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="06447ef8"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
398
LAB2/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0.vhd
Normal file
398
LAB2/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0.vhd
Normal file
@@ -0,0 +1,398 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Bridge FT245Async to AXI4-Stream. --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library xpm;
|
||||
use xpm.vcomponents.all;
|
||||
|
||||
entity AXI4Stream_UART_v1_0 is
|
||||
generic (
|
||||
------------------UART PARAMETER-------------------
|
||||
UART_BAUD_RATE : positive := 115_200;
|
||||
UART_CLOCK_FREQUENCY : positive := 100_000_000; --The associated clock frequency
|
||||
----------------------------------------------------
|
||||
|
||||
-- Parameters of Axi Master Bus Interface M00_AXIS_RX
|
||||
C_M00_AXIS_RX_TDATA_WIDTH : integer := 8;
|
||||
-- Parameters of Axi Slave Bus Interface S00_AXIS_TX
|
||||
C_S00_AXIS_TX_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
---------Global---------
|
||||
clk_uart : IN STD_LOGIC;
|
||||
rst : IN STD_LOGIC;
|
||||
------------------------
|
||||
|
||||
---------Connessioni comunicazione UART-----------
|
||||
UART_TX : OUT STD_LOGIC;
|
||||
UART_RX : IN STD_LOGIC;
|
||||
---------------------------------------------------
|
||||
|
||||
---Ports of Axi Master Bus Interface M00_AXIS_RX---
|
||||
m00_axis_rx_aclk : IN STD_LOGIC;
|
||||
m00_axis_rx_aresetn : IN STD_LOGIC;
|
||||
m00_axis_rx_tvalid : OUT STD_LOGIC;
|
||||
m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0);
|
||||
m00_axis_rx_tready : IN STD_LOGIC;
|
||||
--------------------------------------------------
|
||||
---Ports of Axi Slave Bus Interface S00_AXIS_TX---
|
||||
s00_axis_tx_aclk : IN STD_LOGIC;
|
||||
s00_axis_tx_aresetn : IN STD_LOGIC;
|
||||
s00_axis_tx_tready : OUT STD_LOGIC;
|
||||
s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0);
|
||||
s00_axis_tx_tvalid : IN STD_LOGIC
|
||||
--------------------------------------------------
|
||||
);
|
||||
end AXI4Stream_UART_v1_0;
|
||||
|
||||
architecture arch_imp of AXI4Stream_UART_v1_0 is
|
||||
|
||||
--------------------------------COMPONENTS DECLARATION-----------------------------------
|
||||
component UART_Manager is
|
||||
generic(
|
||||
UART_BAUD_RATE : positive;
|
||||
UART_CLOCK_FREQUENCY : positive --The associated clock frequency
|
||||
);
|
||||
Port (
|
||||
---------Global---------
|
||||
clk_uart : IN STD_LOGIC;
|
||||
reset : IN STD_LOGIC;
|
||||
------------------------
|
||||
|
||||
---------Connessioni comunicazione UART-----------
|
||||
UART_TX : OUT STD_LOGIC;
|
||||
UART_RX : IN STD_LOGIC;
|
||||
---------------------------------------------------
|
||||
|
||||
------------FIFO_DATA_RX (8bit)-------------
|
||||
FIFO_DATA_RX_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_full : IN STD_LOGIC;
|
||||
FIFO_DATA_RX_almost_full : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
------------FIFO_DATA_TX (8bit)-------------
|
||||
--FIFO_DATA_RX_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_empty : IN STD_LOGIC;
|
||||
FIFO_DATA_TX_almost_empty : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end component UART_Manager;
|
||||
|
||||
component AXI4Stream_UART_v1_0_M00_AXIS_RX is
|
||||
generic (
|
||||
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
|
||||
C_M_AXIS_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
--------------FIFO_DATA (8bit)--------------
|
||||
--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
|
||||
FIFO_DATA_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_rd_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_empty : IN STD_LOGIC;
|
||||
FIFO_DATA_almost_empty : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream Clock
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
-- AXI4Stream Reset
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
-- TREADY indicates that the slave can accept a transfer in the current cycle.
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end component AXI4Stream_UART_v1_0_M00_AXIS_RX;
|
||||
|
||||
component AXI4Stream_UART_v1_0_S00_AXIS_TX is
|
||||
generic (
|
||||
-- AXI4Stream sink: Data Width
|
||||
C_S_AXIS_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
|
||||
--------------FIFO_DATA-------------
|
||||
FIFO_DATA_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
FIFO_DATA_wr_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_full : IN STD_LOGIC;
|
||||
FIFO_DATA_almost_full : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream sink: Clock
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
-- AXI4Stream sink: Reset
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
-- Ready to accept data in
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
-- Data in
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
-- Data is in valid
|
||||
S_AXIS_TVALID : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end component AXI4Stream_UART_v1_0_S00_AXIS_TX;
|
||||
-----------------------------------------------------------------------------------------
|
||||
|
||||
---------------------------------------SIGNALS-------------------------------------------
|
||||
-----------------FIFO_DATA_RX-----------------
|
||||
signal FIFO_DATA_RX_rst : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_wr_clk : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_rd_clk : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
signal FIFO_DATA_RX_wr_en : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_rd_en : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
signal FIFO_DATA_RX_full : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_almost_full : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_empty : STD_LOGIC;
|
||||
signal FIFO_DATA_RX_almost_empty : STD_LOGIC;
|
||||
----------------------------------------------
|
||||
|
||||
-----------------FIFO_DATA_TX-----------------
|
||||
signal FIFO_DATA_TX_rst : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_wr_clk : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_rd_clk : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
signal FIFO_DATA_TX_wr_en : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_rd_en : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
signal FIFO_DATA_TX_full : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_almost_full : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_empty : STD_LOGIC;
|
||||
signal FIFO_DATA_TX_almost_empty : STD_LOGIC;
|
||||
----------------------------------------------
|
||||
|
||||
-----------------------------------------------------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
-----------------------MODULE INSTANTIATION-------------------------
|
||||
AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX
|
||||
generic map(
|
||||
-- AXI4Stream sink: Data Width
|
||||
C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TX_TDATA_WIDTH
|
||||
)
|
||||
port map(
|
||||
|
||||
--------------FIFO_DATA-------------
|
||||
FIFO_DATA_rst => FIFO_DATA_TX_rst,
|
||||
FIFO_DATA_clk => FIFO_DATA_TX_wr_clk,
|
||||
FIFO_DATA_din => FIFO_DATA_TX_din,
|
||||
FIFO_DATA_wr_en => FIFO_DATA_TX_wr_en,
|
||||
FIFO_DATA_full => FIFO_DATA_TX_full,
|
||||
FIFO_DATA_almost_full => FIFO_DATA_TX_almost_full,
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream sink: Clock
|
||||
S_AXIS_ACLK => s00_axis_tx_aclk,
|
||||
-- AXI4Stream sink: Reset
|
||||
S_AXIS_ARESETN => s00_axis_tx_aresetn,
|
||||
-- Ready to accept data in
|
||||
S_AXIS_TREADY => s00_axis_tx_tready,
|
||||
-- Data in
|
||||
S_AXIS_TDATA => s00_axis_tx_tdata,
|
||||
-- Data is in valid
|
||||
S_AXIS_TVALID => s00_axis_tx_tvalid
|
||||
--------------------------------------------
|
||||
);
|
||||
|
||||
-- xpm_fifo_async: Asynchronous FIFO
|
||||
-- Xilinx Parameterized Macro, Version 2017.3
|
||||
FIFO_DATA_TX : xpm_fifo_async
|
||||
generic map (
|
||||
FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
|
||||
FIFO_WRITE_DEPTH => 2048, --positive integer;
|
||||
RELATED_CLOCKS => 0, --positive integer; 0 or 1;
|
||||
WRITE_DATA_WIDTH => 8, --positive integer;
|
||||
WR_DATA_COUNT_WIDTH => 1, --positive integer;
|
||||
READ_MODE => "fwft", --string; "std" or "fwft";
|
||||
FIFO_READ_LATENCY => 0, --positive integer;
|
||||
--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
|
||||
READ_DATA_WIDTH => 8, --positive integer;
|
||||
RD_DATA_COUNT_WIDTH => 1, --positive integer;
|
||||
CDC_SYNC_STAGES => 2, --positive integer;
|
||||
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
|
||||
--PROG_FULL_THRESH => 10, --positive integer
|
||||
--PROG_EMPTY_THRESH => 10, --positive integer
|
||||
--DOUT_RESET_VALUE => "0", --string
|
||||
WAKEUP_TIME => 0, --positive integer; 0 or 2;
|
||||
USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
|
||||
)
|
||||
port map (
|
||||
wr_clk => FIFO_DATA_TX_wr_clk,
|
||||
wr_en => FIFO_DATA_TX_wr_en,
|
||||
din => FIFO_DATA_TX_din,
|
||||
full => FIFO_DATA_TX_full,
|
||||
overflow => open,
|
||||
wr_rst_busy => open,
|
||||
sleep => '0',
|
||||
rst => FIFO_DATA_TX_rst,
|
||||
rd_clk => FIFO_DATA_TX_rd_clk,
|
||||
rd_en => FIFO_DATA_TX_rd_en,
|
||||
dout => FIFO_DATA_TX_dout,
|
||||
empty => FIFO_DATA_TX_empty,
|
||||
underflow => open,
|
||||
rd_rst_busy => open,
|
||||
injectsbiterr => '0',
|
||||
injectdbiterr => '0',
|
||||
almost_full => FIFO_DATA_TX_almost_full,
|
||||
almost_empty => FIFO_DATA_TX_almost_empty
|
||||
);
|
||||
|
||||
UART_Manager_inst : UART_Manager
|
||||
Generic map(
|
||||
UART_BAUD_RATE => UART_BAUD_RATE,
|
||||
UART_CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
|
||||
)
|
||||
Port map(
|
||||
---------Global---------
|
||||
clk_uart => clk_uart,
|
||||
reset => rst,
|
||||
------------------------
|
||||
|
||||
---------Connessioni comunicazione UART-----------
|
||||
UART_TX => UART_TX,
|
||||
UART_RX => UART_RX,
|
||||
---------------------------------------------------
|
||||
|
||||
------------FIFO_DATA_RX (8bit)-------------
|
||||
FIFO_DATA_RX_rst => FIFO_DATA_RX_rst,
|
||||
FIFO_DATA_RX_clk => FIFO_DATA_RX_wr_clk,
|
||||
FIFO_DATA_RX_din => FIFO_DATA_RX_din,
|
||||
FIFO_DATA_RX_wr_en => FIFO_DATA_RX_wr_en,
|
||||
FIFO_DATA_RX_full => FIFO_DATA_RX_full,
|
||||
FIFO_DATA_RX_almost_full => FIFO_DATA_RX_almost_full,
|
||||
--------------------------------------------
|
||||
|
||||
------------FIFO_DATA_TX (8bit)-------------
|
||||
FIFO_DATA_TX_clk => FIFO_DATA_TX_rd_clk,
|
||||
FIFO_DATA_TX_dout => FIFO_DATA_TX_dout,
|
||||
FIFO_DATA_TX_rd_en => FIFO_DATA_TX_rd_en,
|
||||
FIFO_DATA_TX_empty => FIFO_DATA_TX_empty,
|
||||
FIFO_DATA_TX_almost_empty => FIFO_DATA_TX_almost_empty
|
||||
--------------------------------------------
|
||||
);
|
||||
|
||||
-- xpm_fifo_async: Asynchronous FIFO
|
||||
-- Xilinx Parameterized Macro, Version 2017.3
|
||||
FIFO_DATA_RX : xpm_fifo_async
|
||||
generic map (
|
||||
FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
|
||||
FIFO_WRITE_DEPTH => 2048, --positive integer;
|
||||
RELATED_CLOCKS => 0, --positive integer; 0 or 1;
|
||||
WRITE_DATA_WIDTH => 8, --positive integer;
|
||||
WR_DATA_COUNT_WIDTH => 1, --positive integer;
|
||||
READ_MODE => "fwft", --string; "std" or "fwft";
|
||||
FIFO_READ_LATENCY => 0, --positive integer;
|
||||
--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
|
||||
READ_DATA_WIDTH => 8, --positive integer;
|
||||
RD_DATA_COUNT_WIDTH => 1, --positive integer;
|
||||
CDC_SYNC_STAGES => 2, --positive integer;
|
||||
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
|
||||
--PROG_FULL_THRESH => 10, --positive integer
|
||||
--PROG_EMPTY_THRESH => 10, --positive integer
|
||||
--DOUT_RESET_VALUE => "0", --string
|
||||
WAKEUP_TIME => 0, --positive integer; 0 or 2;
|
||||
USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
|
||||
)
|
||||
port map (
|
||||
wr_clk => FIFO_DATA_RX_wr_clk,
|
||||
wr_en => FIFO_DATA_RX_wr_en,
|
||||
din => FIFO_DATA_RX_din,
|
||||
full => FIFO_DATA_RX_full,
|
||||
overflow => open,
|
||||
wr_rst_busy => open,
|
||||
sleep => '0',
|
||||
rst => FIFO_DATA_RX_rst,
|
||||
rd_clk => FIFO_DATA_RX_rd_clk,
|
||||
rd_en => FIFO_DATA_RX_rd_en,
|
||||
dout => FIFO_DATA_RX_dout,
|
||||
empty => FIFO_DATA_RX_empty,
|
||||
underflow => open,
|
||||
rd_rst_busy => open,
|
||||
injectsbiterr => '0',
|
||||
injectdbiterr => '0',
|
||||
almost_full => FIFO_DATA_RX_almost_full,
|
||||
almost_empty => FIFO_DATA_RX_almost_empty
|
||||
);
|
||||
|
||||
AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX
|
||||
generic map(
|
||||
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
|
||||
C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_RX_TDATA_WIDTH
|
||||
|
||||
)
|
||||
port map(
|
||||
--------------FIFO_DATA (8bit)--------------
|
||||
FIFO_DATA_clk => FIFO_DATA_RX_rd_clk,
|
||||
FIFO_DATA_dout => FIFO_DATA_RX_dout,
|
||||
FIFO_DATA_rd_en => FIFO_DATA_RX_rd_en,
|
||||
FIFO_DATA_empty => FIFO_DATA_RX_empty,
|
||||
FIFO_DATA_almost_empty => FIFO_DATA_RX_almost_empty,
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream Clock
|
||||
M_AXIS_ACLK => m00_axis_rx_aclk,
|
||||
-- AXI4Stream Reset
|
||||
M_AXIS_ARESETN => m00_axis_rx_aresetn,
|
||||
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
|
||||
M_AXIS_TVALID => m00_axis_rx_tvalid,
|
||||
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
|
||||
M_AXIS_TDATA => m00_axis_rx_tdata,
|
||||
-- TREADY indicates that the slave can accept a transfer in the current cycle.
|
||||
M_AXIS_TREADY => m00_axis_rx_tready
|
||||
--------------------------------------------
|
||||
);
|
||||
|
||||
--------------------------------------------------------------------
|
||||
|
||||
end arch_imp;
|
||||
@@ -0,0 +1,91 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Bridge da FIFO 8bit to AXI4 Stream. --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity AXI4Stream_UART_v1_0_M00_AXIS_RX is
|
||||
generic (
|
||||
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
|
||||
C_M_AXIS_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
--------------FIFO_DATA (8bit)--------------
|
||||
--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
|
||||
FIFO_DATA_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_rd_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_empty : IN STD_LOGIC;
|
||||
FIFO_DATA_almost_empty : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream Clock
|
||||
M_AXIS_ACLK : IN STD_LOGIC;
|
||||
-- AXI4Stream Reset
|
||||
M_AXIS_ARESETN : IN STD_LOGIC;
|
||||
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
|
||||
M_AXIS_TVALID : OUT STD_LOGIC;
|
||||
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
|
||||
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
-- TREADY indicates that the slave can accept a transfer in the current cycle.
|
||||
M_AXIS_TREADY : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end AXI4Stream_UART_v1_0_M00_AXIS_RX;
|
||||
|
||||
architecture implementation of AXI4Stream_UART_v1_0_M00_AXIS_RX is
|
||||
|
||||
----------------------------SIGNALS-----------------------------
|
||||
signal M_AXIS_TVALID_int : STD_LOGIC;
|
||||
----------------------------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
---------DIRECT ASSIGNMENT----------
|
||||
FIFO_DATA_clk <= M_AXIS_ACLK;
|
||||
--FIFO_DATA_rst <= not M_AXIS_ARESETN;
|
||||
|
||||
M_AXIS_TDATA <= FIFO_DATA_dout;
|
||||
|
||||
FIFO_DATA_rd_en <= M_AXIS_TREADY and M_AXIS_TVALID_int;
|
||||
|
||||
M_AXIS_TVALID_int <= not FIFO_DATA_empty and M_AXIS_ARESETN;
|
||||
M_AXIS_TVALID <= M_AXIS_TVALID_int;
|
||||
|
||||
------------------------------------
|
||||
|
||||
end implementation;
|
||||
@@ -0,0 +1,90 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Bridge da FIFO 8bit to AXI4 Stream. --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity AXI4Stream_UART_v1_0_S00_AXIS_TX is
|
||||
generic (
|
||||
-- AXI4Stream sink: Data Width
|
||||
C_S_AXIS_TDATA_WIDTH : integer := 8
|
||||
);
|
||||
port (
|
||||
|
||||
--------------FIFO_DATA (32bit)-------------
|
||||
FIFO_DATA_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
FIFO_DATA_wr_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_full : IN STD_LOGIC;
|
||||
FIFO_DATA_almost_full : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
----------------AXI4-Stream-----------------
|
||||
-- AXI4Stream sink: Clock
|
||||
S_AXIS_ACLK : IN STD_LOGIC;
|
||||
-- AXI4Stream sink: Reset
|
||||
S_AXIS_ARESETN : IN STD_LOGIC;
|
||||
-- Ready to accept data in
|
||||
S_AXIS_TREADY : OUT STD_LOGIC;
|
||||
-- Data in
|
||||
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
|
||||
-- Data is in valid
|
||||
S_AXIS_TVALID : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end AXI4Stream_UART_v1_0_S00_AXIS_TX;
|
||||
|
||||
architecture arch_imp of AXI4Stream_UART_v1_0_S00_AXIS_TX is
|
||||
|
||||
-----------------------------SIGNALS----------------------------
|
||||
signal S_AXIS_TREADY_int : STD_LOGIC;
|
||||
----------------------------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
---------DIRECT ASSIGNMENT----------
|
||||
FIFO_DATA_clk <= S_AXIS_ACLK;
|
||||
FIFO_DATA_rst <= not S_AXIS_ARESETN;
|
||||
|
||||
FIFO_DATA_din <= S_AXIS_TDATA;
|
||||
|
||||
FIFO_DATA_wr_en <= S_AXIS_TREADY_int and S_AXIS_TVALID;
|
||||
|
||||
S_AXIS_TREADY_int <= not FIFO_DATA_almost_full and S_AXIS_ARESETN;
|
||||
S_AXIS_TREADY <= S_AXIS_TREADY_int;
|
||||
------------------------------------
|
||||
|
||||
end arch_imp;
|
||||
343
LAB2/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd
Normal file
343
LAB2/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd
Normal file
@@ -0,0 +1,343 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:02:15 01/23/2016
|
||||
-- Design Name:
|
||||
-- Module Name: uart - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
-- UART
|
||||
-- Implements a universal asynchronous receiver transmitter
|
||||
-------------------------------------------------------------------------------
|
||||
-- clock
|
||||
-- Input clock, must match frequency value given on clock_frequency
|
||||
-- generic input.
|
||||
-- reset
|
||||
-- Synchronous reset.
|
||||
-- data_stream_in
|
||||
-- Input data bus for bytes to transmit.
|
||||
-- data_stream_in_stb
|
||||
-- Input strobe to qualify the input data bus.
|
||||
-- data_stream_in_ack
|
||||
-- Output acknowledge to indicate the UART has begun sending the byte
|
||||
-- provided on the data_stream_in port.
|
||||
-- data_stream_in_done
|
||||
-- Output pulse che arriva quando fine tx
|
||||
-- data_stream_out
|
||||
-- Data output port for received bytes.
|
||||
-- data_stream_out_stb
|
||||
-- Output strobe to qualify the received byte. Will be valid for one clock
|
||||
-- cycle only.
|
||||
-- tx
|
||||
-- Serial transmit.
|
||||
-- rx
|
||||
-- Serial receive
|
||||
-------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity UART_Engine is
|
||||
generic (
|
||||
BAUD_RATE : integer range 110 to 2000000;
|
||||
CLOCK_FREQUENCY : positive
|
||||
);
|
||||
port (
|
||||
clock : in std_logic;
|
||||
reset : in std_logic;
|
||||
data_stream_in : in std_logic_vector(7 downto 0);
|
||||
data_stream_in_stb : in std_logic;
|
||||
data_stream_in_ack : out std_logic;
|
||||
data_stream_in_done : out std_logic;
|
||||
data_stream_out : out std_logic_vector(7 downto 0);
|
||||
data_stream_out_stb : out std_logic;
|
||||
tx : out std_logic;
|
||||
rx : in std_logic
|
||||
);
|
||||
end UART_Engine;
|
||||
|
||||
architecture rtl of UART_Engine is
|
||||
---------------------------------------------------------------------------
|
||||
-- Baud generation constants
|
||||
---------------------------------------------------------------------------
|
||||
constant c_tx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE)));
|
||||
constant c_rx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16)));
|
||||
---------------------------------------------------------------------------
|
||||
-- Baud generation signals
|
||||
---------------------------------------------------------------------------
|
||||
signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0;
|
||||
signal tx_baud_tick : std_logic := '0';
|
||||
signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0;
|
||||
signal rx_baud_tick : std_logic := '0';
|
||||
---------------------------------------------------------------------------
|
||||
-- Transmitter signals
|
||||
---------------------------------------------------------------------------
|
||||
type uart_tx_states is (
|
||||
tx_send_start_bit,
|
||||
tx_send_data,
|
||||
tx_send_stop_bit
|
||||
);
|
||||
signal uart_tx_state : uart_tx_states := tx_send_start_bit;
|
||||
signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal uart_tx_data : std_logic := '1';
|
||||
signal uart_tx_count : unsigned(2 downto 0) := (others => '0');
|
||||
signal uart_rx_data_in_ack : std_logic := '0';
|
||||
signal uart_rx_data_in_done : std_logic := '0';
|
||||
---------------------------------------------------------------------------
|
||||
-- Receiver signals
|
||||
---------------------------------------------------------------------------
|
||||
type uart_rx_states is (
|
||||
rx_get_start_bit,
|
||||
rx_get_data,
|
||||
rx_get_stop_bit
|
||||
);
|
||||
signal uart_rx_state : uart_rx_states := rx_get_start_bit;
|
||||
signal uart_rx_bit : std_logic := '1';
|
||||
signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1');
|
||||
signal uart_rx_filter : unsigned(1 downto 0) := (others => '1');
|
||||
signal uart_rx_count : unsigned(2 downto 0) := (others => '0');
|
||||
signal uart_rx_data_out_stb : std_logic := '0';
|
||||
signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
|
||||
signal uart_rx_bit_tick : std_logic := '0';
|
||||
begin
|
||||
-- Connect IO
|
||||
data_stream_in_ack <= uart_rx_data_in_ack;
|
||||
data_stream_in_done <= uart_rx_data_in_done;
|
||||
data_stream_out <= uart_rx_data_vec;
|
||||
data_stream_out_stb <= uart_rx_data_out_stb;
|
||||
tx <= uart_tx_data;
|
||||
---------------------------------------------------------------------------
|
||||
-- OVERSAMPLE_CLOCK_DIVIDER
|
||||
-- generate an oversampled tick (baud * 16)
|
||||
---------------------------------------------------------------------------
|
||||
oversample_clock_divider : process (clock)
|
||||
begin
|
||||
if rising_edge (clock) then
|
||||
if reset = '1' then
|
||||
rx_baud_counter <= 0;
|
||||
rx_baud_tick <= '0';
|
||||
else
|
||||
if rx_baud_counter = c_rx_div - 1 then
|
||||
rx_baud_counter <= 0;
|
||||
rx_baud_tick <= '1';
|
||||
else
|
||||
rx_baud_counter <= rx_baud_counter + 1;
|
||||
rx_baud_tick <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process oversample_clock_divider;
|
||||
---------------------------------------------------------------------------
|
||||
-- RXD_SYNCHRONISE
|
||||
-- Synchronise rxd to the oversampled baud
|
||||
---------------------------------------------------------------------------
|
||||
rxd_synchronise : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_rx_data_sr <= (others => '1');
|
||||
else
|
||||
if rx_baud_tick = '1' then
|
||||
uart_rx_data_sr(0) <= rx;
|
||||
uart_rx_data_sr(1) <= uart_rx_data_sr(0);
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process rxd_synchronise;
|
||||
---------------------------------------------------------------------------
|
||||
-- RXD_FILTER
|
||||
-- Filter rxd with a 2 bit counter.
|
||||
---------------------------------------------------------------------------
|
||||
rxd_filter : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_rx_filter <= (others => '1');
|
||||
uart_rx_bit <= '1';
|
||||
else
|
||||
if rx_baud_tick = '1' then
|
||||
-- filter rxd.
|
||||
if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then
|
||||
uart_rx_filter <= uart_rx_filter + 1;
|
||||
elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
|
||||
uart_rx_filter <= uart_rx_filter - 1;
|
||||
end if;
|
||||
-- set the rx bit.
|
||||
if uart_rx_filter = 3 then
|
||||
uart_rx_bit <= '1';
|
||||
elsif uart_rx_filter = 0 then
|
||||
uart_rx_bit <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process rxd_filter;
|
||||
---------------------------------------------------------------------------
|
||||
-- RX_BIT_SPACING
|
||||
---------------------------------------------------------------------------
|
||||
rx_bit_spacing : process (clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
uart_rx_bit_tick <= '0';
|
||||
if rx_baud_tick = '1' then
|
||||
if uart_rx_bit_spacing = 15 then
|
||||
uart_rx_bit_tick <= '1';
|
||||
uart_rx_bit_spacing <= (others => '0');
|
||||
else
|
||||
uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
|
||||
end if;
|
||||
if uart_rx_state = rx_get_start_bit then
|
||||
uart_rx_bit_spacing <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process rx_bit_spacing;
|
||||
---------------------------------------------------------------------------
|
||||
-- UART_RECEIVE_DATA
|
||||
---------------------------------------------------------------------------
|
||||
uart_receive_data : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_rx_state <= rx_get_start_bit;
|
||||
uart_rx_data_vec <= (others => '0');
|
||||
uart_rx_count <= (others => '0');
|
||||
uart_rx_data_out_stb <= '0';
|
||||
else
|
||||
uart_rx_data_out_stb <= '0';
|
||||
case uart_rx_state is
|
||||
when rx_get_start_bit =>
|
||||
if rx_baud_tick = '1' and uart_rx_bit = '0' then
|
||||
uart_rx_state <= rx_get_data;
|
||||
end if;
|
||||
when rx_get_data =>
|
||||
if uart_rx_bit_tick = '1' then
|
||||
uart_rx_data_vec(uart_rx_data_vec'high)
|
||||
<= uart_rx_bit;
|
||||
uart_rx_data_vec(
|
||||
uart_rx_data_vec'high-1 downto 0
|
||||
) <= uart_rx_data_vec(
|
||||
uart_rx_data_vec'high downto 1
|
||||
);
|
||||
if uart_rx_count < 7 then
|
||||
uart_rx_count <= uart_rx_count + 1;
|
||||
else
|
||||
uart_rx_count <= (others => '0');
|
||||
uart_rx_state <= rx_get_stop_bit;
|
||||
end if;
|
||||
end if;
|
||||
when rx_get_stop_bit =>
|
||||
if uart_rx_bit_tick = '1' then
|
||||
if uart_rx_bit = '1' then
|
||||
uart_rx_state <= rx_get_start_bit;
|
||||
uart_rx_data_out_stb <= '1';
|
||||
end if;
|
||||
end if;
|
||||
when others =>
|
||||
uart_rx_state <= rx_get_start_bit;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process uart_receive_data;
|
||||
---------------------------------------------------------------------------
|
||||
-- TX_CLOCK_DIVIDER
|
||||
-- Generate baud ticks at the required rate based on the input clock
|
||||
-- frequency and baud rate
|
||||
---------------------------------------------------------------------------
|
||||
tx_clock_divider : process (clock)
|
||||
begin
|
||||
if rising_edge (clock) then
|
||||
if reset = '1' then
|
||||
tx_baud_counter <= 0;
|
||||
tx_baud_tick <= '0';
|
||||
else
|
||||
if tx_baud_counter = c_tx_div - 1 then
|
||||
tx_baud_counter <= 0;
|
||||
tx_baud_tick <= '1';
|
||||
else
|
||||
tx_baud_counter <= tx_baud_counter + 1;
|
||||
tx_baud_tick <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process tx_clock_divider;
|
||||
---------------------------------------------------------------------------
|
||||
-- UART_SEND_DATA
|
||||
-- Get data from data_stream_in and send it one bit at a time upon each
|
||||
-- baud tick. Send data lsb first.
|
||||
-- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1)
|
||||
---------------------------------------------------------------------------
|
||||
uart_send_data : process(clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
if reset = '1' then
|
||||
uart_tx_data <= '1';
|
||||
uart_tx_data_vec <= (others => '0');
|
||||
uart_tx_count <= (others => '0');
|
||||
uart_tx_state <= tx_send_start_bit;
|
||||
uart_rx_data_in_ack <= '0';
|
||||
uart_rx_data_in_done <= '0';
|
||||
else
|
||||
uart_rx_data_in_ack <= '0';
|
||||
uart_rx_data_in_done <= '0'; --new
|
||||
case uart_tx_state is
|
||||
when tx_send_start_bit =>
|
||||
if tx_baud_tick = '1' and data_stream_in_stb = '1' then
|
||||
uart_tx_data <= '0';
|
||||
uart_tx_state <= tx_send_data;
|
||||
uart_tx_count <= (others => '0');
|
||||
uart_rx_data_in_ack <= '1';
|
||||
uart_tx_data_vec <= data_stream_in;
|
||||
end if;
|
||||
when tx_send_data =>
|
||||
if tx_baud_tick = '1' then
|
||||
uart_tx_data <= uart_tx_data_vec(0);
|
||||
uart_tx_data_vec(
|
||||
uart_tx_data_vec'high-1 downto 0
|
||||
) <= uart_tx_data_vec(
|
||||
uart_tx_data_vec'high downto 1
|
||||
);
|
||||
if uart_tx_count < 7 then
|
||||
uart_tx_count <= uart_tx_count + 1;
|
||||
else
|
||||
uart_tx_count <= (others => '0');
|
||||
uart_tx_state <= tx_send_stop_bit;
|
||||
end if;
|
||||
end if;
|
||||
when tx_send_stop_bit =>
|
||||
if tx_baud_tick = '1' then
|
||||
uart_tx_data <= '1';
|
||||
uart_tx_state <= tx_send_start_bit;
|
||||
uart_rx_data_in_done <= '1'; --new
|
||||
end if;
|
||||
when others =>
|
||||
uart_tx_data <= '1';
|
||||
uart_tx_state <= tx_send_start_bit;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process uart_send_data;
|
||||
end rtl;
|
||||
238
LAB2/ip/AXI4-Stream_UART/hdl/UART_Manager.vhd
Normal file
238
LAB2/ip/AXI4-Stream_UART/hdl/UART_Manager.vhd
Normal file
@@ -0,0 +1,238 @@
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
---- * ) ----
|
||||
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
|
||||
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
|
||||
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
|
||||
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
|
||||
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
|
||||
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
|
||||
---- |___/ |___/ ----
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
---- _____ _ ___ __ _ _ _ __ _ ----
|
||||
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
|
||||
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
|
||||
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
|
||||
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
|
||||
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
-------------------------------------DESCRIPTION------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
-- Modulo di pi<70> basso livello per la gestione dei dati tra FIFO in e FIFO out ed il --
|
||||
-- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorit<69> <20> data ai dati in --
|
||||
-- arrivo dal PC verso FPGA. --
|
||||
-- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi --
|
||||
-- rischiesti dal 2232H --
|
||||
------------------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity UART_Manager is
|
||||
generic(
|
||||
UART_BAUD_RATE : positive;
|
||||
UART_CLOCK_FREQUENCY : positive --The associated clock frequency
|
||||
);
|
||||
Port (
|
||||
---------Global---------
|
||||
clk_uart : IN STD_LOGIC;
|
||||
reset : IN STD_LOGIC;
|
||||
------------------------
|
||||
|
||||
---------Connessioni comunicazione UART-----------
|
||||
UART_TX : OUT STD_LOGIC;
|
||||
UART_RX : IN STD_LOGIC;
|
||||
---------------------------------------------------
|
||||
|
||||
------------FIFO_DATA_RX (8bit)-------------
|
||||
FIFO_DATA_RX_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_RX_full : IN STD_LOGIC;
|
||||
FIFO_DATA_RX_almost_full : IN STD_LOGIC;
|
||||
--------------------------------------------
|
||||
|
||||
------------FIFO_DATA_TX (8bit)-------------
|
||||
--FIFO_DATA_RX_rst : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_clk : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
|
||||
FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
|
||||
FIFO_DATA_TX_empty : IN STD_LOGIC;
|
||||
FIFO_DATA_TX_almost_empty : IN STD_LOGIC
|
||||
--------------------------------------------
|
||||
);
|
||||
end UART_Manager;
|
||||
|
||||
architecture Behavioral of UART_Manager is
|
||||
|
||||
-------------------COMPONENT------------------
|
||||
COMPONENT UART_engine
|
||||
GENERIC(
|
||||
BAUD_RATE : positive;
|
||||
CLOCK_FREQUENCY : positive
|
||||
);
|
||||
PORT(
|
||||
--SYSTEM UART
|
||||
clock : IN std_logic;
|
||||
reset : IN std_logic;
|
||||
|
||||
-- FPGA-->PC
|
||||
data_stream_in : IN std_logic_vector(7 downto 0);
|
||||
data_stream_in_stb : IN std_logic;
|
||||
data_stream_in_ack : OUT std_logic;
|
||||
data_stream_in_done : OUT std_logic;
|
||||
tx : OUT std_logic;
|
||||
|
||||
-- PC-->FPGA
|
||||
data_stream_out : OUT std_logic_vector(7 downto 0);
|
||||
data_stream_out_stb : OUT std_logic;
|
||||
rx : IN std_logic
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
----------------------------------------------
|
||||
|
||||
--------------------SIGNALS-------------------
|
||||
signal state : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00";
|
||||
|
||||
--TX:fromFPGAtoPC
|
||||
signal data_stream_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
|
||||
signal data_stream_in_stb : STD_LOGIC := '0';
|
||||
signal data_stream_in_ack : STD_LOGIC := '0';
|
||||
signal data_stream_in_done : STD_LOGIC := '0';
|
||||
|
||||
signal state_TX : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
|
||||
|
||||
--RX:fromPCtoFPGA
|
||||
signal data_stream_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
|
||||
signal data_stream_out_stb : STD_LOGIC := '0';
|
||||
----------------------------------------------
|
||||
|
||||
begin
|
||||
|
||||
Inst_uart: UART_engine
|
||||
GENERIC MAP (
|
||||
BAUD_RATE => UART_BAUD_RATE,
|
||||
CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
|
||||
)
|
||||
PORT MAP(
|
||||
clock => clk_uart,
|
||||
reset => reset,
|
||||
|
||||
-- FPGA-->PC
|
||||
data_stream_in => data_stream_in, --byte FPGA->PC, (in)
|
||||
data_stream_in_stb => data_stream_in_stb, --'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in)
|
||||
data_stream_in_ack => data_stream_in_ack, --'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') <20> stata capita (in)
|
||||
data_stream_in_done => data_stream_in_done, --'1' indica la fine della trasmisione (out)
|
||||
tx => UART_TX,
|
||||
|
||||
-- PC-->FPGA
|
||||
data_stream_out => data_stream_out, --byte PC->FPGA, (out)
|
||||
data_stream_out_stb => data_stream_out_stb, --'1' per 1 clock indica che su data_stream_out c'<27> un nuovo dato (out)
|
||||
-- data_stream_out => FIFO_RX_din,
|
||||
-- data_stream_out_stb => FIFO_RX_wr_en,
|
||||
rx => UART_RX
|
||||
|
||||
);
|
||||
|
||||
fromFPGAtoPC : process(clk_uart, reset)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
state_TX <= x"00";
|
||||
--UART
|
||||
data_stream_in <= (others => '0');
|
||||
data_stream_in_stb <= '0';
|
||||
--FIFO_TX
|
||||
FIFO_DATA_TX_rd_en <= '0';
|
||||
|
||||
elsif rising_edge(clk_uart) then
|
||||
case state_TX is
|
||||
|
||||
when x"FF" =>
|
||||
if(reset = '0') then
|
||||
state_TX <= x"00";
|
||||
else
|
||||
state_TX <= x"FF";
|
||||
end if;
|
||||
--UART
|
||||
data_stream_in <= (others => '0');
|
||||
data_stream_in_stb <= '0';
|
||||
--FIFO_TX
|
||||
FIFO_DATA_TX_rd_en <= '0';
|
||||
|
||||
|
||||
when x"00" =>
|
||||
FIFO_DATA_TX_rd_en <= '0';
|
||||
data_stream_in_stb <= '0';
|
||||
|
||||
if (FIFO_DATA_TX_empty = '0') then --nessun dato da trasmettere al PC
|
||||
state_TX <= x"01"; --si hanno dati in FIFO TX da passare al PC
|
||||
FIFO_DATA_TX_rd_en <= '1'; --abilita lettura FIFO
|
||||
data_stream_in <= FIFO_DATA_TX_dout; --dai alla UART il byte in uscita dalla fifo gi<67> pronto
|
||||
data_stream_in_stb <= '1'; --abilita TX della UART
|
||||
end if;
|
||||
|
||||
|
||||
when x"01" =>
|
||||
FIFO_DATA_TX_rd_en <= '0'; --blocca la lettura FIFO
|
||||
--tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0'
|
||||
if (data_stream_in_ack = '1') then
|
||||
state_TX <= x"02";
|
||||
data_stream_in_stb <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
when x"02" =>
|
||||
-- data_stream_in_done = '1' significa fin trasmisisone UART
|
||||
if (data_stream_in_done = '1') then
|
||||
state_TX <= x"00";
|
||||
end if;
|
||||
|
||||
|
||||
when others =>
|
||||
state_TX <= x"00";
|
||||
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
fromPCtoFPGA : process(clk_uart, reset)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
FIFO_DATA_RX_din <= (others => '0');
|
||||
FIFO_DATA_RX_wr_en <= '0';
|
||||
|
||||
elsif rising_edge(clk_uart) then
|
||||
FIFO_DATA_RX_wr_en <= '0';
|
||||
if (data_stream_out_stb = '1') then --arrivato nuovo dato sulla UART, caricalo in FIGO RX
|
||||
FIFO_DATA_RX_wr_en <= '1';
|
||||
FIFO_DATA_RX_din <= data_stream_out;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
--------------------ASSIGMENT------------------
|
||||
FIFO_DATA_RX_clk <= clk_uart;
|
||||
FIFO_DATA_TX_clk <= clk_uart;
|
||||
|
||||
FIFO_DATA_RX_rst <= reset;
|
||||
-----------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
17
LAB2/ip/AXI4-Stream_UART/utils/board/board.xit
Normal file
17
LAB2/ip/AXI4-Stream_UART/utils/board/board.xit
Normal file
@@ -0,0 +1,17 @@
|
||||
package require xilinx::board 1.0
|
||||
namespace import ::xilinx::board::*
|
||||
|
||||
set instname [current_inst]
|
||||
set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc]
|
||||
puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n"
|
||||
if { [get_project_property BOARD] == "" } {
|
||||
close_ipfile $f_xdc
|
||||
return
|
||||
}
|
||||
|
||||
set board_if [get_property PARAM_VALUE.UART_BOARD_INTERFACE]
|
||||
if { $board_if ne "Custom"} {
|
||||
board_add_port_constraints $f_xdc $board_if TxD UART_TX
|
||||
board_add_port_constraints $f_xdc $board_if RxD UART_RX
|
||||
}
|
||||
close_ipfile $f_xdc
|
||||
36
LAB2/ip/AXI4-Stream_UART/vv_index.xml
Normal file
36
LAB2/ip/AXI4-Stream_UART/vv_index.xml
Normal file
@@ -0,0 +1,36 @@
|
||||
<?xml version="1.0"?>
|
||||
<Index Version="1" Minor="0">
|
||||
<Repository value="/home/nicola/Documents/vivado/axi4-stream-uart">
|
||||
</Repository>
|
||||
<IP>
|
||||
<VLNV value="xilinx.com:user:AXI4Stream_UART:1.0">
|
||||
</VLNV>
|
||||
<DisplayName value="AXI4-Stream UART">
|
||||
</DisplayName>
|
||||
<Description value="AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output">
|
||||
</Description>
|
||||
<CoreRevision value="8">
|
||||
</CoreRevision>
|
||||
<ComponentPath value="component.xml">
|
||||
</ComponentPath>
|
||||
<Families>
|
||||
<Family name="artix7">
|
||||
<Part status="Production" name="ALL">
|
||||
</Part>
|
||||
</Family>
|
||||
<Family name="zynq">
|
||||
<Part status="Production" name="ALL">
|
||||
</Part>
|
||||
</Family>
|
||||
</Families>
|
||||
<Taxonomies>
|
||||
<Taxonomy value="AXI_Peripheral">
|
||||
</Taxonomy>
|
||||
</Taxonomies>
|
||||
<Interfaces>
|
||||
<Interface value="AXI4-Stream">
|
||||
</Interface>
|
||||
</Interfaces>
|
||||
</IP>
|
||||
</Index>
|
||||
|
||||
85
LAB2/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl
Normal file
85
LAB2/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl
Normal file
@@ -0,0 +1,85 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Settings [ipgui::add_page $IPINST -name "Settings"]
|
||||
ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
|
||||
# Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
|
||||
# Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
|
||||
# Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
|
||||
# Procedure called to validate UART_BAUD_RATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
|
||||
# Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
|
||||
# Procedure called to validate UART_CLOCK_FREQUENCY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
|
||||
# Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
|
||||
# Procedure called to validate USE_BOARD_FLOW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
|
||||
# Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
|
||||
# Procedure called to validate UART_BOARD_INTERFACE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}
|
||||
}
|
||||
|
||||
85
LAB2/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl
Normal file
85
LAB2/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl
Normal file
@@ -0,0 +1,85 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Settings [ipgui::add_page $IPINST -name "Settings"]
|
||||
ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
|
||||
# Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
|
||||
# Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
|
||||
# Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
|
||||
# Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
|
||||
# Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
|
||||
# Procedure called to validate UART_BAUD_RATE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
|
||||
# Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
|
||||
# Procedure called to validate UART_CLOCK_FREQUENCY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
|
||||
# Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
|
||||
# Procedure called to validate USE_BOARD_FLOW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
|
||||
# Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
|
||||
# Procedure called to validate UART_BOARD_INTERFACE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}
|
||||
}
|
||||
|
||||
49
LAB2/src/lab_2/hdl/lab_2_wrapper.vhd
Normal file
49
LAB2/src/lab_2/hdl/lab_2_wrapper.vhd
Normal file
@@ -0,0 +1,49 @@
|
||||
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------
|
||||
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
|
||||
--Date : Mon Mar 31 15:19:19 2025
|
||||
--Host : Davide-Samsung running 64-bit major release (build 9200)
|
||||
--Command : generate_target lab_2_wrapper.bd
|
||||
--Design : lab_2_wrapper
|
||||
--Purpose : IP block netlist
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity lab_2_wrapper is
|
||||
port (
|
||||
led_of : out STD_LOGIC;
|
||||
led_ok : out STD_LOGIC;
|
||||
led_uf : out STD_LOGIC;
|
||||
reset : in STD_LOGIC;
|
||||
sys_clock : in STD_LOGIC;
|
||||
usb_uart_rxd : in STD_LOGIC;
|
||||
usb_uart_txd : out STD_LOGIC
|
||||
);
|
||||
end lab_2_wrapper;
|
||||
|
||||
architecture STRUCTURE of lab_2_wrapper is
|
||||
component lab_2 is
|
||||
port (
|
||||
reset : in STD_LOGIC;
|
||||
sys_clock : in STD_LOGIC;
|
||||
led_of : out STD_LOGIC;
|
||||
led_ok : out STD_LOGIC;
|
||||
led_uf : out STD_LOGIC;
|
||||
usb_uart_txd : out STD_LOGIC;
|
||||
usb_uart_rxd : in STD_LOGIC
|
||||
);
|
||||
end component lab_2;
|
||||
begin
|
||||
lab_2_i: component lab_2
|
||||
port map (
|
||||
led_of => led_of,
|
||||
led_ok => led_ok,
|
||||
led_uf => led_uf,
|
||||
reset => reset,
|
||||
sys_clock => sys_clock,
|
||||
usb_uart_rxd => usb_uart_rxd,
|
||||
usb_uart_txd => usb_uart_txd
|
||||
);
|
||||
end STRUCTURE;
|
||||
1317
LAB2/src/lab_2/lab_2.bd
Normal file
1317
LAB2/src/lab_2/lab_2.bd
Normal file
File diff suppressed because it is too large
Load Diff
42
LAB2/src/lab_2/lab_2.bda
Normal file
42
LAB2/src/lab_2/lab_2.bda
Normal file
@@ -0,0 +1,42 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
|
||||
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
|
||||
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
|
||||
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
|
||||
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
|
||||
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
|
||||
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
|
||||
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
|
||||
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
|
||||
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
|
||||
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
|
||||
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
|
||||
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
|
||||
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
|
||||
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
|
||||
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
|
||||
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
|
||||
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
|
||||
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
|
||||
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
|
||||
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
|
||||
<node id="n0">
|
||||
<data key="VH">2</data>
|
||||
<data key="VM">lab_2</data>
|
||||
<data key="VT">VR</data>
|
||||
</node>
|
||||
<node id="n1">
|
||||
<data key="VM">lab_2</data>
|
||||
<data key="VT">BC</data>
|
||||
</node>
|
||||
<node id="n2">
|
||||
<data key="TU">active</data>
|
||||
<data key="VH">2</data>
|
||||
<data key="VT">PM</data>
|
||||
</node>
|
||||
<edge id="e0" source="n1" target="n0">
|
||||
</edge>
|
||||
<edge id="e1" source="n0" target="n2">
|
||||
</edge>
|
||||
</graph>
|
||||
</graphml>
|
||||
Binary file not shown.
BIN
LAB2/test/LAB2-Test_new.exe
Normal file
BIN
LAB2/test/LAB2-Test_new.exe
Normal file
Binary file not shown.
BIN
LAB2/test/test3.png
Normal file
BIN
LAB2/test/test3.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 51 KiB |
648
LAB2/vivado/lab2/lab2.xpr
Normal file
648
LAB2/vivado/lab2/lab2.xpr
Normal file
@@ -0,0 +1,648 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2020.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/lab2/lab2.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="db9fe5dfd4764fe1a8165b98aae70864"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirIES" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../ip"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="4"/>
|
||||
<Option Name="WTModelSimExportSim" Val="4"/>
|
||||
<Option Name="WTQuestaExportSim" Val="4"/>
|
||||
<Option Name="WTIesExportSim" Val="4"/>
|
||||
<Option Name="WTVcsExportSim" Val="4"/>
|
||||
<Option Name="WTRivieraExportSim" Val="4"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="4"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../src/bram_writer.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/depacketizer.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/packetizer.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/rgb2gray.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/led_blinker.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/img_conv.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/lab_2/lab_2.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/lab_2/hdl/lab_2_wrapper.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../src/bram_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="lab_2_wrapper"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../../cons/pins.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="lab_2_wrapper"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_bram_writer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_bram_writer_0_0" RelGenDir="$PGENDIR/lab_2_bram_writer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_bram_writer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_depacketizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_depacketizer_0_0" RelGenDir="$PGENDIR/lab_2_depacketizer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_depacketizer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_packetizer_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_packetizer_0_0" RelGenDir="$PGENDIR/lab_2_packetizer_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_packetizer_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_rgb2gray_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_rgb2gray_0_0" RelGenDir="$PGENDIR/lab_2_rgb2gray_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_rgb2gray_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_led_blinker_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_led_blinker_0_0" RelGenDir="$PGENDIR/lab_2_led_blinker_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_led_blinker_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_img_conv_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_img_conv_0_0" RelGenDir="$PGENDIR/lab_2_img_conv_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_img_conv_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_led_blinker_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_led_blinker_1_0" RelGenDir="$PGENDIR/lab_2_led_blinker_1_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_led_blinker_1_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_led_blinker_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_led_blinker_2_0" RelGenDir="$PGENDIR/lab_2_led_blinker_2_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_led_blinker_2_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_clk_wiz_0_0" RelGenDir="$PGENDIR/lab_2_clk_wiz_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_clk_wiz_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_proc_sys_reset_0_0" RelGenDir="$PGENDIR/lab_2_proc_sys_reset_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_proc_sys_reset_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/lab_2_AXI4Stream_UART_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_AXI4Stream_UART_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="lab_2_system_ila_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lab_2_system_ila_0_1" RelGenDir="$PGENDIR/lab_2_system_ila_0_1">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="lab_2_system_ila_0_1"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="15">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_bram_writer_0_0_synth_1" Type="Ft3:Synth" SrcSet="lab_2_bram_writer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_bram_writer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/lab_2_bram_writer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_bram_writer_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_depacketizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="lab_2_depacketizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_depacketizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/lab_2_depacketizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_depacketizer_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_packetizer_0_0_synth_1" Type="Ft3:Synth" SrcSet="lab_2_packetizer_0_0" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_packetizer_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/lab_2_packetizer_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_packetizer_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_proc_sys_reset_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_proc_sys_reset_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_proc_sys_reset_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_proc_sys_reset_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_AXI4Stream_UART_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_AXI4Stream_UART_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_AXI4Stream_UART_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="lab_2_system_ila_0_1_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="lab_2_system_ila_0_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lab_2_system_ila_0_1_synth_1" IncludeInArchive="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/lab_2_system_ila_0_1_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user