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Add new AXI4-Stream UART IP and update .gitignore for Lab2 files

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This commit is contained in:
Davide Cavagnola
2025-03-31 18:35:29 +02:00
parent 06afed32a3
commit cd5d1b8a0c
19 changed files with 4304 additions and 2 deletions
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36
LAB2/ip/AXI4-Stream_UART/vv_index.xml Normal file
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<?xml version="1.0"?>
<Index Version="1" Minor="0">
<Repository value="/home/nicola/Documents/vivado/axi4-stream-uart">
</Repository>
<IP>
<VLNV value="xilinx.com:user:AXI4Stream_UART:1.0">
</VLNV>
<DisplayName value="AXI4-Stream UART">
</DisplayName>
<Description value="AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output">
</Description>
<CoreRevision value="8">
</CoreRevision>
<ComponentPath value="component.xml">
</ComponentPath>
<Families>
<Family name="artix7">
<Part status="Production" name="ALL">
</Part>
</Family>
<Family name="zynq">
<Part status="Production" name="ALL">
</Part>
</Family>
</Families>
<Taxonomies>
<Taxonomy value="AXI_Peripheral">
</Taxonomy>
</Taxonomies>
<Interfaces>
<Interface value="AXI4-Stream">
</Interface>
</Interfaces>
</IP>
</Index>