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Add new AXI4-Stream UART IP and update .gitignore for Lab2 files

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This commit is contained in:
Davide Cavagnola
2025-03-31 18:35:29 +02:00
parent 06afed32a3
commit cd5d1b8a0c
19 changed files with 4304 additions and 2 deletions
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49
LAB2/src/lab_2/hdl/lab_2_wrapper.vhd Normal file
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon Mar 31 15:19:19 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lab_2_wrapper is
port (
led_of : out STD_LOGIC;
led_ok : out STD_LOGIC;
led_uf : out STD_LOGIC;
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end lab_2_wrapper;
architecture STRUCTURE of lab_2_wrapper is
component lab_2 is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
led_of : out STD_LOGIC;
led_ok : out STD_LOGIC;
led_uf : out STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component lab_2;
begin
lab_2_i: component lab_2
port map (
led_of => led_of,
led_ok => led_ok,
led_uf => led_uf,
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
end STRUCTURE;

1317
LAB2/src/lab_2/lab_2.bd Normal file
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LAB2/src/lab_2/lab_2.bda Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">lab_2</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>