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Refactor project structure and update dependencies

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- Updated .gitignore to exclude virtual environment and additional test files.
- Modified diligent_jstk.bd to reorganize interface nets for clarity.
- Adjusted diligent_jstk.bda to correct node attributes and edges.
- Revised diligent_jstk_wrapper.vhd to ensure proper port declarations.
- Enhanced uart_viewer.py for improved image handling and serial connection checks.
- Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations.
- Added requirements.txt to specify project dependencies for Python packages.
This commit is contained in:
Davide Cavagnola
2025-05-30 14:14:25 +02:00
parent e21c00512f
commit d156d1c944
8 changed files with 189 additions and 119 deletions
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26
LAB3/design/diligent_jstk/diligent_jstk.bd
View File

@@ -591,13 +591,6 @@
}
},
"interface_nets": {
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
@@ -610,10 +603,17 @@
"axi4stream_spi_master_0/SPI_M"
]
},
"AXI4Stream_UART_0_UART": {
"axi4stream_spi_master_0_M_AXIS": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
"axi4stream_spi_master_0/M_AXIS",
"digilent_jstk2_0/s_axis",
"system_ila_0/SLOT_1_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
]
},
"digilent_jstk2_0_m_axis": {
@@ -623,10 +623,10 @@
"system_ila_0/SLOT_0_AXIS"
]
},
"jstk_uart_bridge_0_m_axis": {
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"AXI4Stream_UART_0/S00_AXIS_TX",
"jstk_uart_bridge_0/m_axis"
"usb_uart",
"AXI4Stream_UART_0/UART"
]
}
},

22
LAB3/design/diligent_jstk/diligent_jstk.bda
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@@ -21,22 +21,22 @@
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<node id="n1">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n2">
<data key="VH">2</data>
<data key="VM">diligent_jstk</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n0" target="n2">
<node id="n1">
<data key="VM">diligent_jstk</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n2" target="n1">
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>

10
LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd
View File

@@ -1,8 +1,8 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Mon May 19 09:11:39 2025
--Host : Davide-Samsung running 64-bit major release (build 9200)
--Date : Fri May 30 13:56:20 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target diligent_jstk_wrapper.bd
--Design : diligent_jstk_wrapper
--Purpose : IP block netlist
@@ -29,8 +29,6 @@ architecture STRUCTURE of diligent_jstk_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
SPI_M_0_sck_t : out STD_LOGIC;
SPI_M_0_io1_o : out STD_LOGIC;
SPI_M_0_ss_t : out STD_LOGIC;
@@ -42,7 +40,9 @@ architecture STRUCTURE of diligent_jstk_wrapper is
SPI_M_0_sck_o : out STD_LOGIC;
SPI_M_0_ss_i : in STD_LOGIC;
SPI_M_0_io1_i : in STD_LOGIC;
SPI_M_0_io0_i : in STD_LOGIC
SPI_M_0_io0_i : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component diligent_jstk;
component IOBUF is