Update volume_multiplier testbench and adjust simulation settings; refactor balance_controller and effect_selector logic

2025-05-23 11:12:07 +02:00
parent fd7bac0da1
commit d3dd458825
8 changed files with 224 additions and 38 deletions
--- a/LAB3/sim/tb_volume_multiplier.vhd
+++ b/LAB3/sim/tb_volume_multiplier.vhd
@@ -115,7 +115,7 @@ BEGIN
        WAIT UNTIL rising_edge(aclk);

        -- Set volume to mid (no gain/loss)
-        volume <= volume_mem(0);
+        volume <= volume_mem(7);
        WAIT UNTIL rising_edge(aclk);

        -- Send all samples