Update volume_multiplier testbench and adjust simulation settings; refactor balance_controller and effect_selector logic
This commit is contained in:
@@ -115,7 +115,7 @@ BEGIN
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WAIT UNTIL rising_edge(aclk);
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-- Set volume to mid (no gain/loss)
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volume <= volume_mem(0);
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volume <= volume_mem(7);
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WAIT UNTIL rising_edge(aclk);
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-- Send all samples
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@@ -40,9 +40,7 @@ ARCHITECTURE Behavioral OF balance_controller IS
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BEGIN
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-- Assigning the output signals
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m_axis_tvalid <= m_axis_tvalid_int;
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s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn; -- Chiedere e in caso togliere 'AND aresetn'
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s_axis_tready <= m_axis_tready OR NOT m_axis_tvalid_int;
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-- Balance to exp process to avoid changing the balance value when multiplying it for the sample data
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BALANCE_CALC : PROCESS (aclk)
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@@ -56,13 +54,13 @@ BEGIN
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ELSE
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-- Balance left and right channels
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IF unsigned(balance) > (BAL_MID + DEAD_ZONE) THEN
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IF to_integer(unsigned(balance)) > (BAL_MID + DEAD_ZONE) THEN
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left_channel <= to_integer((unsigned(balance) - to_unsigned(BAL_MID + DEAD_ZONE, balance'length)) SRL BALANCE_STEP_2) + 1; -- +1 due to shift approximation defect
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ELSE
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left_channel <= 0;
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END IF;
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IF unsigned(balance) < (BAL_MID - DEAD_ZONE) THEN
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IF to_integer(unsigned(balance)) < (BAL_MID - DEAD_ZONE) THEN
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right_channel <= to_integer((to_unsigned(BAL_MID - DEAD_ZONE, balance'length) - unsigned(balance)) SRL BALANCE_STEP_2) + 1;
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ELSE
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right_channel <= 0;
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@@ -85,9 +83,6 @@ BEGIN
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m_axis_tlast <= '0';
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ELSE
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-- Default output signals
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m_axis_tlast <= '0';
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-- Clear valid flag when master interface is ready
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IF m_axis_tready = '1' THEN
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m_axis_tvalid_int <= '0';
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@@ -35,14 +35,14 @@ BEGIN
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ELSE
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balance <= jstck_x;
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IF effect = '0' THEN
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IF effect = '1' THEN
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-- LFO control
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lfo_period <= jstck_y;
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ELSE
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-- volume/balance control
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volume <= jstck_y;
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lfo_period <= (OTHERS => '0');
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ELSE
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-- LFO control
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lfo_period <= jstck_y;
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END IF;
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@@ -76,9 +76,6 @@ BEGIN
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m_axis_tlast <= '0';
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ELSE
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-- Default output signals
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m_axis_tlast <= '0';
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-- Clear valid flag when master interface is ready
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IF m_axis_tready = '1' THEN
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m_axis_tvalid_int <= '0';
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@@ -90,10 +87,10 @@ BEGIN
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-- Joystick datasheet: (y-axis) a value of 0 when it is tilted all the way down
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-- and a value of 1023 when it is tilted all the way up
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IF volume_exp_mult >= 0 THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(resize(shift_left(signed(s_axis_tdata), volume_exp_mult), m_axis_tdata'LENGTH));
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m_axis_tdata <= STD_LOGIC_VECTOR(shift_left(resize(signed(s_axis_tdata), m_axis_tdata'LENGTH), volume_exp_mult));
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ELSE
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m_axis_tdata <= STD_LOGIC_VECTOR(resize(shift_right(signed(s_axis_tdata), - volume_exp_mult), m_axis_tdata'LENGTH));
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m_axis_tdata <= STD_LOGIC_VECTOR(shift_right(resize(signed(s_axis_tdata), m_axis_tdata'LENGTH), - volume_exp_mult));
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END IF;
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@@ -28,12 +28,15 @@ END volume_saturator;
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ARCHITECTURE Behavioral OF volume_saturator IS
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CONSTANT HIGHER_BOUND_VEC : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := STD_LOGIC_VECTOR(to_signed(HIGHER_BOUND, TDATA_WIDTH));
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CONSTANT LOWER_BOUND_VEC : STD_LOGIC_VECTOR(TDATA_WIDTH - 1 DOWNTO 0) := STD_LOGIC_VECTOR(to_signed(LOWER_BOUND, TDATA_WIDTH));
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SIGNAL m_axis_tvalid_int : STD_LOGIC;
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BEGIN
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-- Output assignments
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m_axis_tvalid <= m_axis_tvalid_int;
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s_axis_tready <= m_axis_tready AND aresetn;
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s_axis_tready <= (m_axis_tready OR NOT m_axis_tvalid_int) AND aresetn;
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PROCESS (aclk)
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BEGIN
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@@ -43,9 +46,8 @@ BEGIN
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IF aresetn = '0' THEN
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m_axis_tvalid_int <= '0';
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m_axis_tlast <= '0';
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m_axis_tdata <= (OTHERS => '0');
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ELSE
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ELSE
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-- Clear valid flag when master interface is ready
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IF m_axis_tready = '1' THEN
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m_axis_tvalid_int <= '0';
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@@ -54,11 +56,11 @@ BEGIN
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-- Handle the data flow
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IF s_axis_tvalid = '1' AND m_axis_tready = '1' THEN
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-- Check if the input data is within the bounds else saturate
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IF signed(s_axis_tdata) > to_signed(HIGHER_BOUND, s_axis_tdata'length) THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(HIGHER_BOUND, TDATA_WIDTH));
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IF signed(s_axis_tdata) > signed(HIGHER_BOUND_VEC) THEN
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m_axis_tdata <= HIGHER_BOUND_VEC;
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ELSIF signed(s_axis_tdata) < to_signed(LOWER_BOUND, s_axis_tdata'length) THEN
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m_axis_tdata <= STD_LOGIC_VECTOR(to_signed(LOWER_BOUND, TDATA_WIDTH));
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ELSIF signed(s_axis_tdata) < signed(LOWER_BOUND_VEC) THEN
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m_axis_tdata <= LOWER_BOUND_VEC;
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ELSE
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m_axis_tdata <= STD_LOGIC_VECTOR(resize(signed(s_axis_tdata), TDATA_WIDTH));
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@@ -47,7 +47,7 @@
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="WTXSimLaunchSim" Val="57"/>
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<Option Name="WTXSimLaunchSim" Val="63"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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@@ -47,7 +47,7 @@
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="WTXSimLaunchSim" Val="55"/>
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<Option Name="WTXSimLaunchSim" Val="61"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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@@ -95,6 +95,7 @@
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../../sim/tb_volume_saturator.vhd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -150,9 +151,7 @@
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<Runs Version="1" Minor="15">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
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<Step Id="synth_design"/>
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
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@@ -161,9 +160,7 @@
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@@ -179,6 +176,186 @@
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<RQSFiles/>
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</Run>
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</Runs>
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<MsgRule>
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Vivado 12-1790"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
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<MsgAttr Name="StringsToMatch" Val="features"/>
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</MsgRule>
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<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
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|
||||
@@ -11,14 +11,14 @@
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0fs"></ZoomStartTime>
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<ZoomEndTime time="258201fs"></ZoomEndTime>
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<Cursor1Time time="135000fs"></Cursor1Time>
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<ZoomEndTime time="259201fs"></ZoomEndTime>
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<Cursor1Time time="135fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="147"></NameColumnWidth>
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<ValueColumnWidth column_width="93"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="12" />
|
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<WVObjectSize size="13" />
|
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<wvobject fp_name="/tb_volume_saturator/aclk" type="logic">
|
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<obj_property name="ElementShortName">aclk</obj_property>
|
||||
<obj_property name="ObjectShortName">aclk</obj_property>
|
||||
@@ -77,4 +77,19 @@
|
||||
<obj_property name="CustomSignalColor">#FFD700</obj_property>
|
||||
<obj_property name="UseCustomSignalColor">true</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="group45" type="group">
|
||||
<obj_property name="label">BOUNDS</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject fp_name="/tb_volume_saturator/uut/HIGHER_BOUND" type="other">
|
||||
<obj_property name="ElementShortName">HIGHER_BOUND</obj_property>
|
||||
<obj_property name="ObjectShortName">HIGHER_BOUND</obj_property>
|
||||
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
<wvobject fp_name="/tb_volume_saturator/uut/LOWER_BOUND" type="other">
|
||||
<obj_property name="ElementShortName">LOWER_BOUND</obj_property>
|
||||
<obj_property name="ObjectShortName">LOWER_BOUND</obj_property>
|
||||
<obj_property name="Radix">SIGNEDDECRADIX</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
||||
Reference in New Issue
Block a user