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Merge pull request 'add LAB2' (#1) from LAB2 into main

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Reviewed by Davide Cavagnola
This commit is contained in:
Davide Cavagnola
2025-04-25 22:46:26 +02:00
parent 58f8384507 31f66ef8d1
commit d64e15836d
56 changed files with 8861 additions and 315 deletions
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17
.gitignore vendored
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@@ -19,8 +19,6 @@
*.tsi *.tsi
*.vcd *.vcd
*.vdi *.vdi
*.xml
*.tcl
*.ltx *.ltx
*.xci *.xci
*.dcp *.dcp
@@ -44,13 +42,15 @@
*.qws *.qws
*.wdf *.wdf
*.lpr *.lpr
*.xdc
*.bxml
# Vivado project directories # Vivado project directories
*.sim/ *.sim/
*.cache/ *.cache/
*.hw/ *.hw/
*.srcs/ *.gen/
.hwdbg/ .hwdbg/
*.ip_user_files/ *.ip_user_files/
.webtalk/ .webtalk/
@@ -68,3 +68,14 @@ vivado*.backup.log
# SDK workspace # SDK workspace
.sdk/ .sdk/
# design files
**/design/**/ipshared/
**/design/**/ip/
**/design/**/sim/
**/design/**/synth/
**/design/**/ui/
**/design/**/hw_handoff/
# Other files
**/test/*.zip

294
LAB2/cons/basys3_master.xdc
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@@ -1,294 +0,0 @@
## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
## Switches
#set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
#set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
#set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
#set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
#set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
#set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
#set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
#set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
## LEDs
#set_property PACKAGE_PIN U16 [get_ports {led[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#set_property PACKAGE_PIN E19 [get_ports {led[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
#set_property PACKAGE_PIN U19 [get_ports {led[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
#set_property PACKAGE_PIN V19 [get_ports {led[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
#set_property PACKAGE_PIN W18 [get_ports {led[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
#set_property PACKAGE_PIN U15 [get_ports {led[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
#set_property PACKAGE_PIN U14 [get_ports {led[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
#set_property PACKAGE_PIN V14 [get_ports {led[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##7 segment display
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
#set_property PACKAGE_PIN V7 [get_ports dp]
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
##Buttons
#set_property PACKAGE_PIN U18 [get_ports btnC]
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
#set_property PACKAGE_PIN T18 [get_ports btnU]
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
#set_property PACKAGE_PIN W19 [get_ports btnL]
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
#set_property PACKAGE_PIN T17 [get_ports btnR]
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
#set_property PACKAGE_PIN U17 [get_ports btnD]
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
##Pmod Header JA
##Sch name = JA1
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
##Sch name = JA2
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
##Sch name = JA3
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
##Sch name = JA4
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
##Sch name = JA7
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
##Sch name = JA8
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
##Sch name = JA9
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
##Sch name = JA10
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
##Pmod Header JB
##Sch name = JB1
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
##Sch name = JB2
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
##Sch name = JB3
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
##Sch name = JB4
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
##Sch name = JB7
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
##Sch name = JB8
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
##Sch name = JB9
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
##Sch name = JB10
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
##Pmod Header JC
##Sch name = JC1
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
##Sch name = JC2
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
##Sch name = JC3
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
##Sch name = JC4
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
##Sch name = JC7
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
##Sch name = JC8
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
##Sch name = JC9
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
##Sch name = JC10
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
##Pmod Header JXADC
##Sch name = XA1_P
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
##VGA Connector
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
#set_property PACKAGE_PIN P19 [get_ports Hsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
#set_property PACKAGE_PIN R19 [get_ports Vsync]
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
##USB-RS232 Interface
#set_property PACKAGE_PIN B18 [get_ports RsRx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
#set_property PACKAGE_PIN A18 [get_ports RsTx]
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
##USB HID (PS/2)
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
#set_property PULLUP true [get_ports PS2Clk]
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
#set_property PULLUP true [get_ports PS2Data]
##Quad SPI Flash
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
##STARTUPE2 primitive.
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]

6
LAB2/cons/pins.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports led_of]
set_property IOSTANDARD LVCMOS33 [get_ports led_ok]
set_property IOSTANDARD LVCMOS33 [get_ports led_uf]
set_property PACKAGE_PIN U16 [get_ports led_of]
set_property PACKAGE_PIN E19 [get_ports led_ok]
set_property PACKAGE_PIN U19 [get_ports led_uf]

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LAB2/design/lab_2/hdl/lab_2_wrapper.vhd Normal file
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@@ -0,0 +1,49 @@
--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 22:08:38 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target lab_2_wrapper.bd
--Design : lab_2_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity lab_2_wrapper is
port (
led_of : out STD_LOGIC;
led_ok : out STD_LOGIC;
led_uf : out STD_LOGIC;
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end lab_2_wrapper;
architecture STRUCTURE of lab_2_wrapper is
component lab_2 is
port (
led_of : out STD_LOGIC;
led_ok : out STD_LOGIC;
led_uf : out STD_LOGIC;
sys_clock : in STD_LOGIC;
reset : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component lab_2;
begin
lab_2_i: component lab_2
port map (
led_of => led_of,
led_ok => led_ok,
led_uf => led_uf,
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
end STRUCTURE;

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<node id="n1">
<data key="VM">lab_2</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="VH">2</data>
<data key="VM">lab_2</data>
<data key="VT">VR</data>
</node>
<edge id="e0" source="n1" target="n2">
</edge>
<edge id="e1" source="n2" target="n0">
</edge>
</graph>
</graphml>

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LAB2/design/loopback/hdl/loopback_wrapper.vhd Normal file
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--Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
--Date : Fri Apr 25 10:52:31 2025
--Host : DavideASUS running 64-bit major release (build 9200)
--Command : generate_target loopback_wrapper.bd
--Design : loopback_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity loopback_wrapper is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_rxd : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC
);
end loopback_wrapper;
architecture STRUCTURE of loopback_wrapper is
component loopback is
port (
reset : in STD_LOGIC;
sys_clock : in STD_LOGIC;
usb_uart_txd : out STD_LOGIC;
usb_uart_rxd : in STD_LOGIC
);
end component loopback;
begin
loopback_i: component loopback
port map (
reset => reset,
sys_clock => sys_clock,
usb_uart_rxd => usb_uart_rxd,
usb_uart_txd => usb_uart_txd
);
end STRUCTURE;

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{
"design": {
"design_info": {
"boundary_crc": "0x9157799052A71E23",
"device": "xc7a35tcpg236-1",
"name": "loopback",
"rev_ctrl_bd_flag": "RevCtrlBdOff",
"synth_flow_mode": "Hierarchical",
"tool_version": "2020.2",
"validated": "true"
},
"design_tree": {
"proc_sys_reset_0": "",
"clk_wiz_0": "",
"AXI4Stream_UART_0": "",
"packetizer_0": "",
"depacketizer_0": ""
},
"interface_ports": {
"usb_uart": {
"mode": "Master",
"vlnv": "xilinx.com:interface:uart_rtl:1.0"
}
},
"ports": {
"reset": {
"type": "rst",
"direction": "I",
"parameters": {
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"POLARITY": {
"value": "ACTIVE_HIGH"
}
}
},
"sys_clock": {
"type": "clk",
"direction": "I",
"parameters": {
"CLK_DOMAIN": {
"value": "loopback_sys_clock",
"value_src": "default"
},
"FREQ_HZ": {
"value": "100000000"
},
"FREQ_TOLERANCE_HZ": {
"value": "0",
"value_src": "default"
},
"INSERT_VIP": {
"value": "0",
"value_src": "default"
},
"PHASE": {
"value": "0.000"
}
}
}
},
"components": {
"proc_sys_reset_0": {
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
"xci_name": "loopback_proc_sys_reset_0_0",
"xci_path": "ip\\loopback_proc_sys_reset_0_0\\loopback_proc_sys_reset_0_0.xci",
"inst_hier_path": "proc_sys_reset_0",
"parameters": {
"RESET_BOARD_INTERFACE": {
"value": "reset"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"clk_wiz_0": {
"vlnv": "xilinx.com:ip:clk_wiz:6.0",
"xci_name": "loopback_clk_wiz_0_0",
"xci_path": "ip\\loopback_clk_wiz_0_0\\loopback_clk_wiz_0_0.xci",
"inst_hier_path": "clk_wiz_0",
"parameters": {
"CLK_IN1_BOARD_INTERFACE": {
"value": "sys_clock"
},
"RESET_BOARD_INTERFACE": {
"value": "reset"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"AXI4Stream_UART_0": {
"vlnv": "DigiLAB:ip:AXI4Stream_UART:1.1",
"xci_name": "loopback_AXI4Stream_UART_0_0",
"xci_path": "ip\\loopback_AXI4Stream_UART_0_0\\loopback_AXI4Stream_UART_0_0.xci",
"inst_hier_path": "AXI4Stream_UART_0",
"parameters": {
"UART_BOARD_INTERFACE": {
"value": "usb_uart"
},
"USE_BOARD_FLOW": {
"value": "true"
}
}
},
"packetizer_0": {
"vlnv": "xilinx.com:module_ref:packetizer:1.0",
"xci_name": "loopback_packetizer_0_0",
"xci_path": "ip\\loopback_packetizer_0_0\\loopback_packetizer_0_0.xci",
"inst_hier_path": "packetizer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "packetizer",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "s_axis_tlast",
"direction": "I"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
},
"depacketizer_0": {
"vlnv": "xilinx.com:module_ref:depacketizer:1.0",
"xci_name": "loopback_depacketizer_0_0",
"xci_path": "ip\\loopback_depacketizer_0_0\\loopback_depacketizer_0_0.xci",
"inst_hier_path": "depacketizer_0",
"reference_info": {
"ref_type": "hdl",
"ref_name": "depacketizer",
"boundary_crc": "0x0"
},
"interface_ports": {
"m_axis": {
"mode": "Master",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "1",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "m_axis_tdata",
"direction": "O",
"left": "7",
"right": "0"
},
"TLAST": {
"physical_name": "m_axis_tlast",
"direction": "O"
},
"TVALID": {
"physical_name": "m_axis_tvalid",
"direction": "O"
},
"TREADY": {
"physical_name": "m_axis_tready",
"direction": "I"
}
}
},
"s_axis": {
"mode": "Slave",
"vlnv": "xilinx.com:interface:axis_rtl:1.0",
"parameters": {
"TDATA_NUM_BYTES": {
"value": "1",
"value_src": "constant"
},
"TDEST_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TID_WIDTH": {
"value": "0",
"value_src": "constant"
},
"TUSER_WIDTH": {
"value": "0",
"value_src": "constant"
},
"HAS_TREADY": {
"value": "1",
"value_src": "constant"
},
"HAS_TSTRB": {
"value": "0",
"value_src": "constant"
},
"HAS_TKEEP": {
"value": "0",
"value_src": "constant"
},
"HAS_TLAST": {
"value": "0",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
},
"port_maps": {
"TDATA": {
"physical_name": "s_axis_tdata",
"direction": "I",
"left": "7",
"right": "0"
},
"TVALID": {
"physical_name": "s_axis_tvalid",
"direction": "I"
},
"TREADY": {
"physical_name": "s_axis_tready",
"direction": "O"
}
}
}
},
"ports": {
"clk": {
"type": "clk",
"direction": "I",
"parameters": {
"ASSOCIATED_BUSIF": {
"value": "m_axis:s_axis",
"value_src": "constant"
},
"ASSOCIATED_RESET": {
"value": "aresetn",
"value_src": "constant"
},
"FREQ_HZ": {
"value": "100000000",
"value_src": "ip_prop"
},
"PHASE": {
"value": "0.0",
"value_src": "ip_prop"
},
"CLK_DOMAIN": {
"value": "/clk_wiz_0_clk_out1",
"value_src": "ip_prop"
}
}
},
"aresetn": {
"type": "rst",
"direction": "I",
"parameters": {
"POLARITY": {
"value": "ACTIVE_LOW",
"value_src": "constant"
}
}
}
}
}
},
"interface_nets": {
"AXI4Stream_UART_0_M00_AXIS_RX": {
"interface_ports": [
"AXI4Stream_UART_0/M00_AXIS_RX",
"depacketizer_0/s_axis"
]
},
"packetizer_0_m_axis": {
"interface_ports": [
"packetizer_0/m_axis",
"AXI4Stream_UART_0/S00_AXIS_TX"
]
},
"AXI4Stream_UART_0_UART": {
"interface_ports": [
"usb_uart",
"AXI4Stream_UART_0/UART"
]
},
"depacketizer_0_m_axis": {
"interface_ports": [
"depacketizer_0/m_axis",
"packetizer_0/s_axis"
]
}
},
"nets": {
"reset_1": {
"ports": [
"reset",
"proc_sys_reset_0/ext_reset_in",
"clk_wiz_0/reset"
]
},
"sys_clock_1": {
"ports": [
"sys_clock",
"clk_wiz_0/clk_in1"
]
},
"clk_wiz_0_clk_out1": {
"ports": [
"clk_wiz_0/clk_out1",
"AXI4Stream_UART_0/clk_uart",
"proc_sys_reset_0/slowest_sync_clk",
"AXI4Stream_UART_0/m00_axis_rx_aclk",
"AXI4Stream_UART_0/s00_axis_tx_aclk",
"packetizer_0/clk",
"depacketizer_0/clk"
]
},
"proc_sys_reset_0_peripheral_reset": {
"ports": [
"proc_sys_reset_0/peripheral_reset",
"AXI4Stream_UART_0/rst"
]
},
"clk_wiz_0_locked": {
"ports": [
"clk_wiz_0/locked",
"proc_sys_reset_0/dcm_locked"
]
},
"proc_sys_reset_0_peripheral_aresetn": {
"ports": [
"proc_sys_reset_0/peripheral_aresetn",
"AXI4Stream_UART_0/m00_axis_rx_aresetn",
"AXI4Stream_UART_0/s00_axis_tx_aresetn",
"packetizer_0/aresetn",
"depacketizer_0/aresetn"
]
}
}
}
}

42
LAB2/design/loopback/loopback.bda Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
<key attr.name="base_addr" attr.type="string" for="node" id="BA"/>
<key attr.name="base_param" attr.type="string" for="node" id="BP"/>
<key attr.name="edge_hid" attr.type="int" for="edge" id="EH"/>
<key attr.name="high_addr" attr.type="string" for="node" id="HA"/>
<key attr.name="high_param" attr.type="string" for="node" id="HP"/>
<key attr.name="master_addrspace" attr.type="string" for="node" id="MA"/>
<key attr.name="master_instance" attr.type="string" for="node" id="MX"/>
<key attr.name="master_interface" attr.type="string" for="node" id="MI"/>
<key attr.name="master_segment" attr.type="string" for="node" id="MS"/>
<key attr.name="master_vlnv" attr.type="string" for="node" id="MV"/>
<key attr.name="memory_type" attr.type="string" for="node" id="TM"/>
<key attr.name="slave_instance" attr.type="string" for="node" id="SX"/>
<key attr.name="slave_interface" attr.type="string" for="node" id="SI"/>
<key attr.name="slave_segment" attr.type="string" for="node" id="SS"/>
<key attr.name="slave_vlnv" attr.type="string" for="node" id="SV"/>
<key attr.name="usage_type" attr.type="string" for="node" id="TU"/>
<key attr.name="vert_hid" attr.type="int" for="node" id="VH"/>
<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
<key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
<graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
<node id="n0">
<data key="VH">2</data>
<data key="VM">loopback</data>
<data key="VT">VR</data>
</node>
<node id="n1">
<data key="VM">loopback</data>
<data key="VT">BC</data>
</node>
<node id="n2">
<data key="TU">active</data>
<data key="VH">2</data>
<data key="VT">PM</data>
</node>
<edge id="e0" source="n1" target="n0">
</edge>
<edge id="e1" source="n0" target="n2">
</edge>
</graph>
</graphml>

89
LAB2/ip/AXI4-Stream_UART/bd/bd.tcl Normal file
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proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
# Set module clock frequency reference to be equal to the input clock.
set_property CONFIG.UART_CLOCK_FREQUENCY [format %d [get_property CONFIG.FREQ_HZ [get_bd_pins $cellpath/clk_uart]]] $cell_handle
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}

765
LAB2/ip/AXI4-Stream_UART/component.xml Normal file
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@@ -0,0 +1,765 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>DigiLAB</spirit:vendor>
<spirit:library>ip</spirit:library>
<spirit:name>AXI4Stream_UART</spirit:name>
<spirit:version>1.1</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>M00_AXIS_RX</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m00_axis_rx_tdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m00_axis_rx_tvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m00_axis_rx_tready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>WIZ_DATA_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.M00_AXIS_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S00_AXIS_TX</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axis_tx_tdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axis_tx_tvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s00_axis_tx_tready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>WIZ_DATA_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXIS_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>M00_AXIS_RX_RST</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">AXI4Stream_UART_v1_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>UART_BAUD_RATE</spirit:name>
<spirit:displayName>Baud Rate</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BAUD_RATE" spirit:choiceRef="choice_list_23c37a81">115200</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>UART_CLOCK_FREQUENCY</spirit:name>
<spirit:displayName>Rs232 Clock Frequency</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UART_CLOCK_FREQUENCY">100000000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_M00_AXIS_RX_TDATA_WIDTH</spirit:name>
<spirit:displayName>C M00 Axis Rx Tdata Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd">8</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_M00_AXIS_RX_TDATA_WIDTH">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S00_AXIS_TX_TDATA_WIDTH</spirit:name>
<spirit:displayName>C S00 Axis Tx Tdata Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>USE_BOARD_FLOW</spirit:name>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1000">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>UART_BOARD_INTERFACE</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.UART_BOARD_INTERFACE" spirit:order="1001">Custom</spirit:value>
</spirit:parameter>
</spirit:parameters>
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<xilinx:coreExtensions>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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<xilinx:taxonomies>
<xilinx:taxonomy>/AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>AXI4-Stream UART</xilinx:displayName>
<xilinx:xpmLibraries>
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
</xilinx:xpmLibraries>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:upgrades>
<xilinx:canUpgradeFrom>TimeEngineers:ip:AXI4Stream_UART:1.0</xilinx:canUpgradeFrom>
</xilinx:upgrades>
<xilinx:coreCreationDateTime>2021-01-15T12:00:01Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b59b4e5a"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="adabba16"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="a9681487"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f305a3bd"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="06447ef8"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>

398
LAB2/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0.vhd Normal file
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@@ -0,0 +1,398 @@
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
---- * ) ----
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
---- |___/ |___/ ----
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
---- _____ _ ___ __ _ _ _ __ _ ----
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------DESCRIPTION------------------------------------------
------------------------------------------------------------------------------------------
-- Bridge FT245Async to AXI4-Stream. --
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library xpm;
use xpm.vcomponents.all;
entity AXI4Stream_UART_v1_0 is
generic (
------------------UART PARAMETER-------------------
UART_BAUD_RATE : positive := 115_200;
UART_CLOCK_FREQUENCY : positive := 100_000_000; --The associated clock frequency
----------------------------------------------------
-- Parameters of Axi Master Bus Interface M00_AXIS_RX
C_M00_AXIS_RX_TDATA_WIDTH : integer := 8;
-- Parameters of Axi Slave Bus Interface S00_AXIS_TX
C_S00_AXIS_TX_TDATA_WIDTH : integer := 8
);
port (
---------Global---------
clk_uart : IN STD_LOGIC;
rst : IN STD_LOGIC;
------------------------
---------Connessioni comunicazione UART-----------
UART_TX : OUT STD_LOGIC;
UART_RX : IN STD_LOGIC;
---------------------------------------------------
---Ports of Axi Master Bus Interface M00_AXIS_RX---
m00_axis_rx_aclk : IN STD_LOGIC;
m00_axis_rx_aresetn : IN STD_LOGIC;
m00_axis_rx_tvalid : OUT STD_LOGIC;
m00_axis_rx_tdata : OUT STD_LOGIC_VECTOR(C_M00_AXIS_RX_TDATA_WIDTH-1 DOWNTO 0);
m00_axis_rx_tready : IN STD_LOGIC;
--------------------------------------------------
---Ports of Axi Slave Bus Interface S00_AXIS_TX---
s00_axis_tx_aclk : IN STD_LOGIC;
s00_axis_tx_aresetn : IN STD_LOGIC;
s00_axis_tx_tready : OUT STD_LOGIC;
s00_axis_tx_tdata : IN STD_LOGIC_VECTOR(C_S00_AXIS_TX_TDATA_WIDTH-1 DOWNTO 0);
s00_axis_tx_tvalid : IN STD_LOGIC
--------------------------------------------------
);
end AXI4Stream_UART_v1_0;
architecture arch_imp of AXI4Stream_UART_v1_0 is
--------------------------------COMPONENTS DECLARATION-----------------------------------
component UART_Manager is
generic(
UART_BAUD_RATE : positive;
UART_CLOCK_FREQUENCY : positive --The associated clock frequency
);
Port (
---------Global---------
clk_uart : IN STD_LOGIC;
reset : IN STD_LOGIC;
------------------------
---------Connessioni comunicazione UART-----------
UART_TX : OUT STD_LOGIC;
UART_RX : IN STD_LOGIC;
---------------------------------------------------
------------FIFO_DATA_RX (8bit)-------------
FIFO_DATA_RX_rst : OUT STD_LOGIC;
FIFO_DATA_RX_clk : OUT STD_LOGIC;
FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
FIFO_DATA_RX_full : IN STD_LOGIC;
FIFO_DATA_RX_almost_full : IN STD_LOGIC;
--------------------------------------------
------------FIFO_DATA_TX (8bit)-------------
--FIFO_DATA_RX_rst : OUT STD_LOGIC;
FIFO_DATA_TX_clk : OUT STD_LOGIC;
FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
FIFO_DATA_TX_empty : IN STD_LOGIC;
FIFO_DATA_TX_almost_empty : IN STD_LOGIC
--------------------------------------------
);
end component UART_Manager;
component AXI4Stream_UART_v1_0_M00_AXIS_RX is
generic (
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
C_M_AXIS_TDATA_WIDTH : integer := 8
);
port (
--------------FIFO_DATA (8bit)--------------
--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
FIFO_DATA_clk : OUT STD_LOGIC;
FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
FIFO_DATA_rd_en : OUT STD_LOGIC;
FIFO_DATA_empty : IN STD_LOGIC;
FIFO_DATA_almost_empty : IN STD_LOGIC;
--------------------------------------------
----------------AXI4-Stream-----------------
-- AXI4Stream Clock
M_AXIS_ACLK : IN STD_LOGIC;
-- AXI4Stream Reset
M_AXIS_ARESETN : IN STD_LOGIC;
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
M_AXIS_TVALID : OUT STD_LOGIC;
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-- TREADY indicates that the slave can accept a transfer in the current cycle.
M_AXIS_TREADY : IN STD_LOGIC
--------------------------------------------
);
end component AXI4Stream_UART_v1_0_M00_AXIS_RX;
component AXI4Stream_UART_v1_0_S00_AXIS_TX is
generic (
-- AXI4Stream sink: Data Width
C_S_AXIS_TDATA_WIDTH : integer := 8
);
port (
--------------FIFO_DATA-------------
FIFO_DATA_rst : OUT STD_LOGIC;
FIFO_DATA_clk : OUT STD_LOGIC;
FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
FIFO_DATA_wr_en : OUT STD_LOGIC;
FIFO_DATA_full : IN STD_LOGIC;
FIFO_DATA_almost_full : IN STD_LOGIC;
--------------------------------------------
----------------AXI4-Stream-----------------
-- AXI4Stream sink: Clock
S_AXIS_ACLK : IN STD_LOGIC;
-- AXI4Stream sink: Reset
S_AXIS_ARESETN : IN STD_LOGIC;
-- Ready to accept data in
S_AXIS_TREADY : OUT STD_LOGIC;
-- Data in
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-- Data is in valid
S_AXIS_TVALID : IN STD_LOGIC
--------------------------------------------
);
end component AXI4Stream_UART_v1_0_S00_AXIS_TX;
-----------------------------------------------------------------------------------------
---------------------------------------SIGNALS-------------------------------------------
-----------------FIFO_DATA_RX-----------------
signal FIFO_DATA_RX_rst : STD_LOGIC;
signal FIFO_DATA_RX_wr_clk : STD_LOGIC;
signal FIFO_DATA_RX_rd_clk : STD_LOGIC;
signal FIFO_DATA_RX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal FIFO_DATA_RX_wr_en : STD_LOGIC;
signal FIFO_DATA_RX_rd_en : STD_LOGIC;
signal FIFO_DATA_RX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal FIFO_DATA_RX_full : STD_LOGIC;
signal FIFO_DATA_RX_almost_full : STD_LOGIC;
signal FIFO_DATA_RX_empty : STD_LOGIC;
signal FIFO_DATA_RX_almost_empty : STD_LOGIC;
----------------------------------------------
-----------------FIFO_DATA_TX-----------------
signal FIFO_DATA_TX_rst : STD_LOGIC;
signal FIFO_DATA_TX_wr_clk : STD_LOGIC;
signal FIFO_DATA_TX_rd_clk : STD_LOGIC;
signal FIFO_DATA_TX_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal FIFO_DATA_TX_wr_en : STD_LOGIC;
signal FIFO_DATA_TX_rd_en : STD_LOGIC;
signal FIFO_DATA_TX_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal FIFO_DATA_TX_full : STD_LOGIC;
signal FIFO_DATA_TX_almost_full : STD_LOGIC;
signal FIFO_DATA_TX_empty : STD_LOGIC;
signal FIFO_DATA_TX_almost_empty : STD_LOGIC;
----------------------------------------------
-----------------------------------------------------------------------------------------
begin
-----------------------MODULE INSTANTIATION-------------------------
AXI4Stream_UART_v1_0_S00_AXIS_TX_inst : AXI4Stream_UART_v1_0_S00_AXIS_TX
generic map(
-- AXI4Stream sink: Data Width
C_S_AXIS_TDATA_WIDTH => C_S00_AXIS_TX_TDATA_WIDTH
)
port map(
--------------FIFO_DATA-------------
FIFO_DATA_rst => FIFO_DATA_TX_rst,
FIFO_DATA_clk => FIFO_DATA_TX_wr_clk,
FIFO_DATA_din => FIFO_DATA_TX_din,
FIFO_DATA_wr_en => FIFO_DATA_TX_wr_en,
FIFO_DATA_full => FIFO_DATA_TX_full,
FIFO_DATA_almost_full => FIFO_DATA_TX_almost_full,
--------------------------------------------
----------------AXI4-Stream-----------------
-- AXI4Stream sink: Clock
S_AXIS_ACLK => s00_axis_tx_aclk,
-- AXI4Stream sink: Reset
S_AXIS_ARESETN => s00_axis_tx_aresetn,
-- Ready to accept data in
S_AXIS_TREADY => s00_axis_tx_tready,
-- Data in
S_AXIS_TDATA => s00_axis_tx_tdata,
-- Data is in valid
S_AXIS_TVALID => s00_axis_tx_tvalid
--------------------------------------------
);
-- xpm_fifo_async: Asynchronous FIFO
-- Xilinx Parameterized Macro, Version 2017.3
FIFO_DATA_TX : xpm_fifo_async
generic map (
FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
FIFO_WRITE_DEPTH => 2048, --positive integer;
RELATED_CLOCKS => 0, --positive integer; 0 or 1;
WRITE_DATA_WIDTH => 8, --positive integer;
WR_DATA_COUNT_WIDTH => 1, --positive integer;
READ_MODE => "fwft", --string; "std" or "fwft";
FIFO_READ_LATENCY => 0, --positive integer;
--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
READ_DATA_WIDTH => 8, --positive integer;
RD_DATA_COUNT_WIDTH => 1, --positive integer;
CDC_SYNC_STAGES => 2, --positive integer;
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
--PROG_FULL_THRESH => 10, --positive integer
--PROG_EMPTY_THRESH => 10, --positive integer
--DOUT_RESET_VALUE => "0", --string
WAKEUP_TIME => 0, --positive integer; 0 or 2;
USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
)
port map (
wr_clk => FIFO_DATA_TX_wr_clk,
wr_en => FIFO_DATA_TX_wr_en,
din => FIFO_DATA_TX_din,
full => FIFO_DATA_TX_full,
overflow => open,
wr_rst_busy => open,
sleep => '0',
rst => FIFO_DATA_TX_rst,
rd_clk => FIFO_DATA_TX_rd_clk,
rd_en => FIFO_DATA_TX_rd_en,
dout => FIFO_DATA_TX_dout,
empty => FIFO_DATA_TX_empty,
underflow => open,
rd_rst_busy => open,
injectsbiterr => '0',
injectdbiterr => '0',
almost_full => FIFO_DATA_TX_almost_full,
almost_empty => FIFO_DATA_TX_almost_empty
);
UART_Manager_inst : UART_Manager
Generic map(
UART_BAUD_RATE => UART_BAUD_RATE,
UART_CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
)
Port map(
---------Global---------
clk_uart => clk_uart,
reset => rst,
------------------------
---------Connessioni comunicazione UART-----------
UART_TX => UART_TX,
UART_RX => UART_RX,
---------------------------------------------------
------------FIFO_DATA_RX (8bit)-------------
FIFO_DATA_RX_rst => FIFO_DATA_RX_rst,
FIFO_DATA_RX_clk => FIFO_DATA_RX_wr_clk,
FIFO_DATA_RX_din => FIFO_DATA_RX_din,
FIFO_DATA_RX_wr_en => FIFO_DATA_RX_wr_en,
FIFO_DATA_RX_full => FIFO_DATA_RX_full,
FIFO_DATA_RX_almost_full => FIFO_DATA_RX_almost_full,
--------------------------------------------
------------FIFO_DATA_TX (8bit)-------------
FIFO_DATA_TX_clk => FIFO_DATA_TX_rd_clk,
FIFO_DATA_TX_dout => FIFO_DATA_TX_dout,
FIFO_DATA_TX_rd_en => FIFO_DATA_TX_rd_en,
FIFO_DATA_TX_empty => FIFO_DATA_TX_empty,
FIFO_DATA_TX_almost_empty => FIFO_DATA_TX_almost_empty
--------------------------------------------
);
-- xpm_fifo_async: Asynchronous FIFO
-- Xilinx Parameterized Macro, Version 2017.3
FIFO_DATA_RX : xpm_fifo_async
generic map (
FIFO_MEMORY_TYPE => "block", --string; "auto", "block", "distributed", or "ultra";
FIFO_WRITE_DEPTH => 2048, --positive integer;
RELATED_CLOCKS => 0, --positive integer; 0 or 1;
WRITE_DATA_WIDTH => 8, --positive integer;
WR_DATA_COUNT_WIDTH => 1, --positive integer;
READ_MODE => "fwft", --string; "std" or "fwft";
FIFO_READ_LATENCY => 0, --positive integer;
--FULL_RESET_VALUE => 0, --positive integer; 0 or 1;
READ_DATA_WIDTH => 8, --positive integer;
RD_DATA_COUNT_WIDTH => 1, --positive integer;
CDC_SYNC_STAGES => 2, --positive integer;
ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc";
--PROG_FULL_THRESH => 10, --positive integer
--PROG_EMPTY_THRESH => 10, --positive integer
--DOUT_RESET_VALUE => "0", --string
WAKEUP_TIME => 0, --positive integer; 0 or 2;
USE_ADV_FEATURES => "0808" --string; "0000" to "1F1F"; 0808 = almost_full and almost_empty
)
port map (
wr_clk => FIFO_DATA_RX_wr_clk,
wr_en => FIFO_DATA_RX_wr_en,
din => FIFO_DATA_RX_din,
full => FIFO_DATA_RX_full,
overflow => open,
wr_rst_busy => open,
sleep => '0',
rst => FIFO_DATA_RX_rst,
rd_clk => FIFO_DATA_RX_rd_clk,
rd_en => FIFO_DATA_RX_rd_en,
dout => FIFO_DATA_RX_dout,
empty => FIFO_DATA_RX_empty,
underflow => open,
rd_rst_busy => open,
injectsbiterr => '0',
injectdbiterr => '0',
almost_full => FIFO_DATA_RX_almost_full,
almost_empty => FIFO_DATA_RX_almost_empty
);
AXI4Stream_UART_v1_0_M00_AXIS_RX_inst : AXI4Stream_UART_v1_0_M00_AXIS_RX
generic map(
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
C_M_AXIS_TDATA_WIDTH => C_M00_AXIS_RX_TDATA_WIDTH
)
port map(
--------------FIFO_DATA (8bit)--------------
FIFO_DATA_clk => FIFO_DATA_RX_rd_clk,
FIFO_DATA_dout => FIFO_DATA_RX_dout,
FIFO_DATA_rd_en => FIFO_DATA_RX_rd_en,
FIFO_DATA_empty => FIFO_DATA_RX_empty,
FIFO_DATA_almost_empty => FIFO_DATA_RX_almost_empty,
--------------------------------------------
----------------AXI4-Stream-----------------
-- AXI4Stream Clock
M_AXIS_ACLK => m00_axis_rx_aclk,
-- AXI4Stream Reset
M_AXIS_ARESETN => m00_axis_rx_aresetn,
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
M_AXIS_TVALID => m00_axis_rx_tvalid,
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
M_AXIS_TDATA => m00_axis_rx_tdata,
-- TREADY indicates that the slave can accept a transfer in the current cycle.
M_AXIS_TREADY => m00_axis_rx_tready
--------------------------------------------
);
--------------------------------------------------------------------
end arch_imp;

91
LAB2/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_M00_AXIS_RX.vhd Normal file
View File

@@ -0,0 +1,91 @@
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
---- * ) ----
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
---- |___/ |___/ ----
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
---- _____ _ ___ __ _ _ _ __ _ ----
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------DESCRIPTION------------------------------------------
------------------------------------------------------------------------------------------
-- Bridge da FIFO 8bit to AXI4 Stream. --
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI4Stream_UART_v1_0_M00_AXIS_RX is
generic (
-- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
C_M_AXIS_TDATA_WIDTH : integer := 8
);
port (
--------------FIFO_DATA (8bit)--------------
--FIFO_DATA_rst : OUT STD_LOGIC; Reset lo da chi scrive la FIFO
FIFO_DATA_clk : OUT STD_LOGIC;
FIFO_DATA_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
FIFO_DATA_rd_en : OUT STD_LOGIC;
FIFO_DATA_empty : IN STD_LOGIC;
FIFO_DATA_almost_empty : IN STD_LOGIC;
--------------------------------------------
----------------AXI4-Stream-----------------
-- AXI4Stream Clock
M_AXIS_ACLK : IN STD_LOGIC;
-- AXI4Stream Reset
M_AXIS_ARESETN : IN STD_LOGIC;
-- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
M_AXIS_TVALID : OUT STD_LOGIC;
-- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(C_M_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-- TREADY indicates that the slave can accept a transfer in the current cycle.
M_AXIS_TREADY : IN STD_LOGIC
--------------------------------------------
);
end AXI4Stream_UART_v1_0_M00_AXIS_RX;
architecture implementation of AXI4Stream_UART_v1_0_M00_AXIS_RX is
----------------------------SIGNALS-----------------------------
signal M_AXIS_TVALID_int : STD_LOGIC;
----------------------------------------------------------------
begin
---------DIRECT ASSIGNMENT----------
FIFO_DATA_clk <= M_AXIS_ACLK;
--FIFO_DATA_rst <= not M_AXIS_ARESETN;
M_AXIS_TDATA <= FIFO_DATA_dout;
FIFO_DATA_rd_en <= M_AXIS_TREADY and M_AXIS_TVALID_int;
M_AXIS_TVALID_int <= not FIFO_DATA_empty and M_AXIS_ARESETN;
M_AXIS_TVALID <= M_AXIS_TVALID_int;
------------------------------------
end implementation;

90
LAB2/ip/AXI4-Stream_UART/hdl/AXI4Stream_UART_v1_0_S00_AXIS_TX.vhd Normal file
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@@ -0,0 +1,90 @@
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
---- * ) ----
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
---- |___/ |___/ ----
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
---- _____ _ ___ __ _ _ _ __ _ ----
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------DESCRIPTION------------------------------------------
------------------------------------------------------------------------------------------
-- Bridge da FIFO 8bit to AXI4 Stream. --
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AXI4Stream_UART_v1_0_S00_AXIS_TX is
generic (
-- AXI4Stream sink: Data Width
C_S_AXIS_TDATA_WIDTH : integer := 8
);
port (
--------------FIFO_DATA (32bit)-------------
FIFO_DATA_rst : OUT STD_LOGIC;
FIFO_DATA_clk : OUT STD_LOGIC;
FIFO_DATA_din : OUT STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
FIFO_DATA_wr_en : OUT STD_LOGIC;
FIFO_DATA_full : IN STD_LOGIC;
FIFO_DATA_almost_full : IN STD_LOGIC;
--------------------------------------------
----------------AXI4-Stream-----------------
-- AXI4Stream sink: Clock
S_AXIS_ACLK : IN STD_LOGIC;
-- AXI4Stream sink: Reset
S_AXIS_ARESETN : IN STD_LOGIC;
-- Ready to accept data in
S_AXIS_TREADY : OUT STD_LOGIC;
-- Data in
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(C_S_AXIS_TDATA_WIDTH-1 DOWNTO 0);
-- Data is in valid
S_AXIS_TVALID : IN STD_LOGIC
--------------------------------------------
);
end AXI4Stream_UART_v1_0_S00_AXIS_TX;
architecture arch_imp of AXI4Stream_UART_v1_0_S00_AXIS_TX is
-----------------------------SIGNALS----------------------------
signal S_AXIS_TREADY_int : STD_LOGIC;
----------------------------------------------------------------
begin
---------DIRECT ASSIGNMENT----------
FIFO_DATA_clk <= S_AXIS_ACLK;
FIFO_DATA_rst <= not S_AXIS_ARESETN;
FIFO_DATA_din <= S_AXIS_TDATA;
FIFO_DATA_wr_en <= S_AXIS_TREADY_int and S_AXIS_TVALID;
S_AXIS_TREADY_int <= not FIFO_DATA_almost_full and S_AXIS_ARESETN;
S_AXIS_TREADY <= S_AXIS_TREADY_int;
------------------------------------
end arch_imp;

343
LAB2/ip/AXI4-Stream_UART/hdl/UART_Engine.vhd Normal file
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:15 01/23/2016
-- Design Name:
-- Module Name: uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- UART
-- Implements a universal asynchronous receiver transmitter
-------------------------------------------------------------------------------
-- clock
-- Input clock, must match frequency value given on clock_frequency
-- generic input.
-- reset
-- Synchronous reset.
-- data_stream_in
-- Input data bus for bytes to transmit.
-- data_stream_in_stb
-- Input strobe to qualify the input data bus.
-- data_stream_in_ack
-- Output acknowledge to indicate the UART has begun sending the byte
-- provided on the data_stream_in port.
-- data_stream_in_done
-- Output pulse che arriva quando fine tx
-- data_stream_out
-- Data output port for received bytes.
-- data_stream_out_stb
-- Output strobe to qualify the received byte. Will be valid for one clock
-- cycle only.
-- tx
-- Serial transmit.
-- rx
-- Serial receive
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UART_Engine is
generic (
BAUD_RATE : integer range 110 to 2000000;
CLOCK_FREQUENCY : positive
);
port (
clock : in std_logic;
reset : in std_logic;
data_stream_in : in std_logic_vector(7 downto 0);
data_stream_in_stb : in std_logic;
data_stream_in_ack : out std_logic;
data_stream_in_done : out std_logic;
data_stream_out : out std_logic_vector(7 downto 0);
data_stream_out_stb : out std_logic;
tx : out std_logic;
rx : in std_logic
);
end UART_Engine;
architecture rtl of UART_Engine is
---------------------------------------------------------------------------
-- Baud generation constants
---------------------------------------------------------------------------
constant c_tx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE)));
constant c_rx_div : integer := integer(round(real(CLOCK_FREQUENCY) / real(BAUD_RATE * 16)));
---------------------------------------------------------------------------
-- Baud generation signals
---------------------------------------------------------------------------
signal tx_baud_counter : integer range 0 to c_tx_div-1 := 0;
signal tx_baud_tick : std_logic := '0';
signal rx_baud_counter : integer range 0 to c_rx_div-1 := 0;
signal rx_baud_tick : std_logic := '0';
---------------------------------------------------------------------------
-- Transmitter signals
---------------------------------------------------------------------------
type uart_tx_states is (
tx_send_start_bit,
tx_send_data,
tx_send_stop_bit
);
signal uart_tx_state : uart_tx_states := tx_send_start_bit;
signal uart_tx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
signal uart_tx_data : std_logic := '1';
signal uart_tx_count : unsigned(2 downto 0) := (others => '0');
signal uart_rx_data_in_ack : std_logic := '0';
signal uart_rx_data_in_done : std_logic := '0';
---------------------------------------------------------------------------
-- Receiver signals
---------------------------------------------------------------------------
type uart_rx_states is (
rx_get_start_bit,
rx_get_data,
rx_get_stop_bit
);
signal uart_rx_state : uart_rx_states := rx_get_start_bit;
signal uart_rx_bit : std_logic := '1';
signal uart_rx_data_vec : std_logic_vector(7 downto 0) := (others => '0');
signal uart_rx_data_sr : std_logic_vector(1 downto 0) := (others => '1');
signal uart_rx_filter : unsigned(1 downto 0) := (others => '1');
signal uart_rx_count : unsigned(2 downto 0) := (others => '0');
signal uart_rx_data_out_stb : std_logic := '0';
signal uart_rx_bit_spacing : unsigned (3 downto 0) := (others => '0');
signal uart_rx_bit_tick : std_logic := '0';
begin
-- Connect IO
data_stream_in_ack <= uart_rx_data_in_ack;
data_stream_in_done <= uart_rx_data_in_done;
data_stream_out <= uart_rx_data_vec;
data_stream_out_stb <= uart_rx_data_out_stb;
tx <= uart_tx_data;
---------------------------------------------------------------------------
-- OVERSAMPLE_CLOCK_DIVIDER
-- generate an oversampled tick (baud * 16)
---------------------------------------------------------------------------
oversample_clock_divider : process (clock)
begin
if rising_edge (clock) then
if reset = '1' then
rx_baud_counter <= 0;
rx_baud_tick <= '0';
else
if rx_baud_counter = c_rx_div - 1 then
rx_baud_counter <= 0;
rx_baud_tick <= '1';
else
rx_baud_counter <= rx_baud_counter + 1;
rx_baud_tick <= '0';
end if;
end if;
end if;
end process oversample_clock_divider;
---------------------------------------------------------------------------
-- RXD_SYNCHRONISE
-- Synchronise rxd to the oversampled baud
---------------------------------------------------------------------------
rxd_synchronise : process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
uart_rx_data_sr <= (others => '1');
else
if rx_baud_tick = '1' then
uart_rx_data_sr(0) <= rx;
uart_rx_data_sr(1) <= uart_rx_data_sr(0);
end if;
end if;
end if;
end process rxd_synchronise;
---------------------------------------------------------------------------
-- RXD_FILTER
-- Filter rxd with a 2 bit counter.
---------------------------------------------------------------------------
rxd_filter : process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
uart_rx_filter <= (others => '1');
uart_rx_bit <= '1';
else
if rx_baud_tick = '1' then
-- filter rxd.
if uart_rx_data_sr(1) = '1' and uart_rx_filter < 3 then
uart_rx_filter <= uart_rx_filter + 1;
elsif uart_rx_data_sr(1) = '0' and uart_rx_filter > 0 then
uart_rx_filter <= uart_rx_filter - 1;
end if;
-- set the rx bit.
if uart_rx_filter = 3 then
uart_rx_bit <= '1';
elsif uart_rx_filter = 0 then
uart_rx_bit <= '0';
end if;
end if;
end if;
end if;
end process rxd_filter;
---------------------------------------------------------------------------
-- RX_BIT_SPACING
---------------------------------------------------------------------------
rx_bit_spacing : process (clock)
begin
if rising_edge(clock) then
uart_rx_bit_tick <= '0';
if rx_baud_tick = '1' then
if uart_rx_bit_spacing = 15 then
uart_rx_bit_tick <= '1';
uart_rx_bit_spacing <= (others => '0');
else
uart_rx_bit_spacing <= uart_rx_bit_spacing + 1;
end if;
if uart_rx_state = rx_get_start_bit then
uart_rx_bit_spacing <= (others => '0');
end if;
end if;
end if;
end process rx_bit_spacing;
---------------------------------------------------------------------------
-- UART_RECEIVE_DATA
---------------------------------------------------------------------------
uart_receive_data : process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
uart_rx_state <= rx_get_start_bit;
uart_rx_data_vec <= (others => '0');
uart_rx_count <= (others => '0');
uart_rx_data_out_stb <= '0';
else
uart_rx_data_out_stb <= '0';
case uart_rx_state is
when rx_get_start_bit =>
if rx_baud_tick = '1' and uart_rx_bit = '0' then
uart_rx_state <= rx_get_data;
end if;
when rx_get_data =>
if uart_rx_bit_tick = '1' then
uart_rx_data_vec(uart_rx_data_vec'high)
<= uart_rx_bit;
uart_rx_data_vec(
uart_rx_data_vec'high-1 downto 0
) <= uart_rx_data_vec(
uart_rx_data_vec'high downto 1
);
if uart_rx_count < 7 then
uart_rx_count <= uart_rx_count + 1;
else
uart_rx_count <= (others => '0');
uart_rx_state <= rx_get_stop_bit;
end if;
end if;
when rx_get_stop_bit =>
if uart_rx_bit_tick = '1' then
if uart_rx_bit = '1' then
uart_rx_state <= rx_get_start_bit;
uart_rx_data_out_stb <= '1';
end if;
end if;
when others =>
uart_rx_state <= rx_get_start_bit;
end case;
end if;
end if;
end process uart_receive_data;
---------------------------------------------------------------------------
-- TX_CLOCK_DIVIDER
-- Generate baud ticks at the required rate based on the input clock
-- frequency and baud rate
---------------------------------------------------------------------------
tx_clock_divider : process (clock)
begin
if rising_edge (clock) then
if reset = '1' then
tx_baud_counter <= 0;
tx_baud_tick <= '0';
else
if tx_baud_counter = c_tx_div - 1 then
tx_baud_counter <= 0;
tx_baud_tick <= '1';
else
tx_baud_counter <= tx_baud_counter + 1;
tx_baud_tick <= '0';
end if;
end if;
end if;
end process tx_clock_divider;
---------------------------------------------------------------------------
-- UART_SEND_DATA
-- Get data from data_stream_in and send it one bit at a time upon each
-- baud tick. Send data lsb first.
-- wait 1 tick, send start bit (0), send data 0-7, send stop bit (1)
---------------------------------------------------------------------------
uart_send_data : process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
uart_tx_data <= '1';
uart_tx_data_vec <= (others => '0');
uart_tx_count <= (others => '0');
uart_tx_state <= tx_send_start_bit;
uart_rx_data_in_ack <= '0';
uart_rx_data_in_done <= '0';
else
uart_rx_data_in_ack <= '0';
uart_rx_data_in_done <= '0'; --new
case uart_tx_state is
when tx_send_start_bit =>
if tx_baud_tick = '1' and data_stream_in_stb = '1' then
uart_tx_data <= '0';
uart_tx_state <= tx_send_data;
uart_tx_count <= (others => '0');
uart_rx_data_in_ack <= '1';
uart_tx_data_vec <= data_stream_in;
end if;
when tx_send_data =>
if tx_baud_tick = '1' then
uart_tx_data <= uart_tx_data_vec(0);
uart_tx_data_vec(
uart_tx_data_vec'high-1 downto 0
) <= uart_tx_data_vec(
uart_tx_data_vec'high downto 1
);
if uart_tx_count < 7 then
uart_tx_count <= uart_tx_count + 1;
else
uart_tx_count <= (others => '0');
uart_tx_state <= tx_send_stop_bit;
end if;
end if;
when tx_send_stop_bit =>
if tx_baud_tick = '1' then
uart_tx_data <= '1';
uart_tx_state <= tx_send_start_bit;
uart_rx_data_in_done <= '1'; --new
end if;
when others =>
uart_tx_data <= '1';
uart_tx_state <= tx_send_start_bit;
end case;
end if;
end if;
end process uart_send_data;
end rtl;

238
LAB2/ip/AXI4-Stream_UART/hdl/UART_Manager.vhd Normal file
View File

@@ -0,0 +1,238 @@
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
---- * ) ----
----` ) /( ( ) ( ( ( ( ( ( ( ( ( ( ( ----
---- ( )(_)))\ ( ))\ )\ ( )\))( )\ ( ))\ ))\ )( )\ ( )\))( ----
----(_(_())((_) )\ ' /((_) ((_) )\ ) ((_))\((_) )\ ) /((_)/((_)(()\((_) )\ ) ((_))\ ----
----|_ _| (_) _((_)) (_)) | __| _(_/( (()(_)(_) _(_/( (_)) (_)) ((_)(_) _(_/( (()(_) ----
---- | | | || ' \()/ -_) | _| | ' \))/ _` | | || ' \))/ -_)/ -_) | '_|| || ' \))/ _` | ----
---- |_| |_||_|_|_| \___| |___||_||_| \__, | |_||_||_| \___|\___| |_| |_||_||_| \__, | ----
---- |___/ |___/ ----
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
---- _____ _ ___ __ _ _ _ __ _ ----
---- o O O |_ _| (_) _ __ ___ | __| _ _ / _` | (_) _ _ ___ ___ _ _ (_) _ _ / _` | ----
---- o | | | | | ' \ / -_) | _| | ' \ \__, | | | | ' \ / -_) / -_) | '_| | | | ' \ \__, | ----
---- TS__[O] _|_|_ _|_|_ |_|_|_| \___| |___| |_||_| |___/ _|_|_ |_||_| \___| \___| _|_|_ _|_|_ |_||_| |___/ ----
---- {======|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""|_|"""""| ----
----./o--000'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-'"`-0-0-' ----
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------DESCRIPTION------------------------------------------
------------------------------------------------------------------------------------------
-- Modulo di più basso livello per la gestione dei dati tra FIFO in e FIFO out ed il --
-- modulo FTDI 2232H in modalita FT245 Asynchronous. La priorità è data ai dati in --
-- arrivo dal PC verso FPGA. --
-- Il clock in ingresso deve avere un periodo di 10 ns per garantire i tempi --
-- rischiesti dal 2232H --
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UART_Manager is
generic(
UART_BAUD_RATE : positive;
UART_CLOCK_FREQUENCY : positive --The associated clock frequency
);
Port (
---------Global---------
clk_uart : IN STD_LOGIC;
reset : IN STD_LOGIC;
------------------------
---------Connessioni comunicazione UART-----------
UART_TX : OUT STD_LOGIC;
UART_RX : IN STD_LOGIC;
---------------------------------------------------
------------FIFO_DATA_RX (8bit)-------------
FIFO_DATA_RX_rst : OUT STD_LOGIC;
FIFO_DATA_RX_clk : OUT STD_LOGIC;
FIFO_DATA_RX_din : OUT STD_LOGIC_VECTOR(8-1 DOWNTO 0);
FIFO_DATA_RX_wr_en : OUT STD_LOGIC;
FIFO_DATA_RX_full : IN STD_LOGIC;
FIFO_DATA_RX_almost_full : IN STD_LOGIC;
--------------------------------------------
------------FIFO_DATA_TX (8bit)-------------
--FIFO_DATA_RX_rst : OUT STD_LOGIC;
FIFO_DATA_TX_clk : OUT STD_LOGIC;
FIFO_DATA_TX_dout : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
FIFO_DATA_TX_rd_en : OUT STD_LOGIC;
FIFO_DATA_TX_empty : IN STD_LOGIC;
FIFO_DATA_TX_almost_empty : IN STD_LOGIC
--------------------------------------------
);
end UART_Manager;
architecture Behavioral of UART_Manager is
-------------------COMPONENT------------------
COMPONENT UART_engine
GENERIC(
BAUD_RATE : positive;
CLOCK_FREQUENCY : positive
);
PORT(
--SYSTEM UART
clock : IN std_logic;
reset : IN std_logic;
-- FPGA-->PC
data_stream_in : IN std_logic_vector(7 downto 0);
data_stream_in_stb : IN std_logic;
data_stream_in_ack : OUT std_logic;
data_stream_in_done : OUT std_logic;
tx : OUT std_logic;
-- PC-->FPGA
data_stream_out : OUT std_logic_vector(7 downto 0);
data_stream_out_stb : OUT std_logic;
rx : IN std_logic
);
END COMPONENT;
----------------------------------------------
--------------------SIGNALS-------------------
signal state : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"00";
--TX:fromFPGAtoPC
signal data_stream_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
signal data_stream_in_stb : STD_LOGIC := '0';
signal data_stream_in_ack : STD_LOGIC := '0';
signal data_stream_in_done : STD_LOGIC := '0';
signal state_TX : STD_LOGIC_VECTOR(7 DOWNTO 0):=x"FF";
--RX:fromPCtoFPGA
signal data_stream_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others=>'0');
signal data_stream_out_stb : STD_LOGIC := '0';
----------------------------------------------
begin
Inst_uart: UART_engine
GENERIC MAP (
BAUD_RATE => UART_BAUD_RATE,
CLOCK_FREQUENCY => UART_CLOCK_FREQUENCY
)
PORT MAP(
clock => clk_uart,
reset => reset,
-- FPGA-->PC
data_stream_in => data_stream_in, --byte FPGA->PC, (in)
data_stream_in_stb => data_stream_in_stb, --'1' per 1 clock inizia la fase di trasmisisone a PC di data_stream_in (in)
data_stream_in_ack => data_stream_in_ack, --'1' per 1 clock vuol dire che START TX (data_stream_in_stb='1') è stata capita (in)
data_stream_in_done => data_stream_in_done, --'1' indica la fine della trasmisione (out)
tx => UART_TX,
-- PC-->FPGA
data_stream_out => data_stream_out, --byte PC->FPGA, (out)
data_stream_out_stb => data_stream_out_stb, --'1' per 1 clock indica che su data_stream_out c'è un nuovo dato (out)
-- data_stream_out => FIFO_RX_din,
-- data_stream_out_stb => FIFO_RX_wr_en,
rx => UART_RX
);
fromFPGAtoPC : process(clk_uart, reset)
begin
if (reset = '1') then
state_TX <= x"00";
--UART
data_stream_in <= (others => '0');
data_stream_in_stb <= '0';
--FIFO_TX
FIFO_DATA_TX_rd_en <= '0';
elsif rising_edge(clk_uart) then
case state_TX is
when x"FF" =>
if(reset = '0') then
state_TX <= x"00";
else
state_TX <= x"FF";
end if;
--UART
data_stream_in <= (others => '0');
data_stream_in_stb <= '0';
--FIFO_TX
FIFO_DATA_TX_rd_en <= '0';
when x"00" =>
FIFO_DATA_TX_rd_en <= '0';
data_stream_in_stb <= '0';
if (FIFO_DATA_TX_empty = '0') then --nessun dato da trasmettere al PC
state_TX <= x"01"; --si hanno dati in FIFO TX da passare al PC
FIFO_DATA_TX_rd_en <= '1'; --abilita lettura FIFO
data_stream_in <= FIFO_DATA_TX_dout; --dai alla UART il byte in uscita dalla fifo già pronto
data_stream_in_stb <= '1'; --abilita TX della UART
end if;
when x"01" =>
FIFO_DATA_TX_rd_en <= '0'; --blocca la lettura FIFO
--tieni data_stream_in_stb attivo finche la UART non inizia a trasferire data_stream_in_ack='0'
if (data_stream_in_ack = '1') then
state_TX <= x"02";
data_stream_in_stb <= '0';
end if;
when x"02" =>
-- data_stream_in_done = '1' significa fin trasmisisone UART
if (data_stream_in_done = '1') then
state_TX <= x"00";
end if;
when others =>
state_TX <= x"00";
end case;
end if;
end process;
fromPCtoFPGA : process(clk_uart, reset)
begin
if (reset = '1') then
FIFO_DATA_RX_din <= (others => '0');
FIFO_DATA_RX_wr_en <= '0';
elsif rising_edge(clk_uart) then
FIFO_DATA_RX_wr_en <= '0';
if (data_stream_out_stb = '1') then --arrivato nuovo dato sulla UART, caricalo in FIGO RX
FIFO_DATA_RX_wr_en <= '1';
FIFO_DATA_RX_din <= data_stream_out;
end if;
end if;
end process;
--------------------ASSIGMENT------------------
FIFO_DATA_RX_clk <= clk_uart;
FIFO_DATA_TX_clk <= clk_uart;
FIFO_DATA_RX_rst <= reset;
-----------------------------------------------
end Behavioral;

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LAB2/ip/AXI4-Stream_UART/utils/board/board.xit Normal file
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package require xilinx::board 1.0
namespace import ::xilinx::board::*
set instname [current_inst]
set f_xdc [add_ipfile -usedIn [list synthesis implementation board ] -force ${instname}_board.xdc]
puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n"
if { [get_project_property BOARD] == "" } {
close_ipfile $f_xdc
return
}
set board_if [get_property PARAM_VALUE.UART_BOARD_INTERFACE]
if { $board_if ne "Custom"} {
board_add_port_constraints $f_xdc $board_if TxD UART_TX
board_add_port_constraints $f_xdc $board_if RxD UART_RX
}
close_ipfile $f_xdc

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LAB2/ip/AXI4-Stream_UART/vv_index.xml Normal file
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<?xml version="1.0"?>
<Index Version="1" Minor="0">
<Repository value="/home/nicola/Documents/vivado/axi4-stream-uart">
</Repository>
<IP>
<VLNV value="xilinx.com:user:AXI4Stream_UART:1.0">
</VLNV>
<DisplayName value="AXI4-Stream UART">
</DisplayName>
<Description value="AXI4-Stream bridge to UART. Internal buffer is 16kb for Input and for Output">
</Description>
<CoreRevision value="8">
</CoreRevision>
<ComponentPath value="component.xml">
</ComponentPath>
<Families>
<Family name="artix7">
<Part status="Production" name="ALL">
</Part>
</Family>
<Family name="zynq">
<Part status="Production" name="ALL">
</Part>
</Family>
</Families>
<Taxonomies>
<Taxonomy value="AXI_Peripheral">
</Taxonomy>
</Taxonomies>
<Interfaces>
<Interface value="AXI4-Stream">
</Interface>
</Interfaces>
</IP>
</Index>

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LAB2/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_0.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Settings [ipgui::add_page $IPINST -name "Settings"]
ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox
}
proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to validate UART_BAUD_RATE
return true
}
proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to validate UART_CLOCK_FREQUENCY
return true
}
proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to validate USE_BOARD_FLOW
return true
}
proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to validate UART_BOARD_INTERFACE
return true
}
proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
}
proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY}
}
proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}
}

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LAB2/ip/AXI4-Stream_UART/xgui/AXI4Stream_UART_v1_1.tcl Normal file
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Settings [ipgui::add_page $IPINST -name "Settings"]
ipgui::add_param $IPINST -name "UART_BAUD_RATE" -parent ${Settings} -widget comboBox
}
proc update_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to update C_M00_AXIS_RX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to validate C_M00_AXIS_RX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to update C_S00_AXIS_TX_TDATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to validate C_S00_AXIS_TX_TDATA_WIDTH
return true
}
proc update_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to update UART_BAUD_RATE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BAUD_RATE { PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to validate UART_BAUD_RATE
return true
}
proc update_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to update UART_CLOCK_FREQUENCY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_CLOCK_FREQUENCY { PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to validate UART_CLOCK_FREQUENCY
return true
}
proc update_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to update USE_BOARD_FLOW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.USE_BOARD_FLOW { PARAM_VALUE.USE_BOARD_FLOW } {
# Procedure called to validate USE_BOARD_FLOW
return true
}
proc update_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to update UART_BOARD_INTERFACE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.UART_BOARD_INTERFACE { PARAM_VALUE.UART_BOARD_INTERFACE } {
# Procedure called to validate UART_BOARD_INTERFACE
return true
}
proc update_MODELPARAM_VALUE.UART_BAUD_RATE { MODELPARAM_VALUE.UART_BAUD_RATE PARAM_VALUE.UART_BAUD_RATE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_BAUD_RATE}] ${MODELPARAM_VALUE.UART_BAUD_RATE}
}
proc update_MODELPARAM_VALUE.UART_CLOCK_FREQUENCY { MODELPARAM_VALUE.UART_CLOCK_FREQUENCY PARAM_VALUE.UART_CLOCK_FREQUENCY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.UART_CLOCK_FREQUENCY}] ${MODELPARAM_VALUE.UART_CLOCK_FREQUENCY}
}
proc update_MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH { MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M00_AXIS_RX_TDATA_WIDTH}
}
proc update_MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH { MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXIS_TX_TDATA_WIDTH}
}

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/17/2025
-- Design Name:
-- Module Name: tb_bram_writer - sim
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Testbench for bram_writer, rewritten in the style of tb_packetizer.vhd
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_bram_writer IS
END tb_bram_writer;
ARCHITECTURE sim OF tb_bram_writer IS
-- Testbench constants
CONSTANT ADDR_WIDTH : POSITIVE := 4;
CONSTANT IMG_SIZE : POSITIVE := 4; -- Increased size for more memory
-- Component declaration for bram_writer
COMPONENT bram_writer IS
GENERIC (
ADDR_WIDTH : POSITIVE;
IMG_SIZE : POSITIVE
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC;
conv_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0);
conv_data : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
start_conv : OUT STD_LOGIC;
done_conv : IN STD_LOGIC;
write_ok : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
underflow : OUT STD_LOGIC
);
END COMPONENT;
-- Signals for DUT
SIGNAL clk : STD_LOGIC := '0';
SIGNAL aresetn : STD_LOGIC := '0';
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axis_tvalid : STD_LOGIC := '0';
SIGNAL s_axis_tready : STD_LOGIC;
SIGNAL s_axis_tlast : STD_LOGIC := '0';
SIGNAL conv_addr : STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL conv_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL start_conv : STD_LOGIC;
SIGNAL done_conv : STD_LOGIC := '0';
SIGNAL write_ok : STD_LOGIC;
SIGNAL overflow : STD_LOGIC;
SIGNAL underflow : STD_LOGIC;
-- Stimulus memory for input data
TYPE mem_type IS ARRAY(0 TO (IMG_SIZE*IMG_SIZE)-1) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mem : mem_type := (
0 => x"3A",
1 => x"7F",
2 => x"12",
3 => x"9C",
4 => x"55",
5 => x"2B",
6 => x"81",
7 => x"04",
8 => x"6E",
9 => x"F2",
10 => x"1D",
11 => x"C7",
12 => x"99",
13 => x"0A",
14 => x"B3",
15 => x"5D"
);
BEGIN
-- Clock generation
clk <= NOT clk AFTER 5 ns;
-- DUT instantiation
uut: bram_writer
GENERIC MAP (
ADDR_WIDTH => ADDR_WIDTH,
IMG_SIZE => IMG_SIZE
)
PORT MAP (
clk => clk,
aresetn => aresetn,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast,
conv_addr => conv_addr,
conv_data => conv_data,
start_conv => start_conv,
done_conv => done_conv,
write_ok => write_ok,
overflow => overflow,
underflow => underflow
);
-- Stimulus process
stimulus : PROCESS
BEGIN
-- Reset
aresetn <= '0';
WAIT FOR 20 ns;
aresetn <= '1';
WAIT UNTIL rising_edge(clk);
-- Send IMG_SIZE*IMG_SIZE data words
FOR i IN 0 TO IMG_SIZE*IMG_SIZE-1 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
IF i = IMG_SIZE*IMG_SIZE-1 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
-- Wait for handshake
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
s_axis_tlast <= '0';
-- Wait for write_ok and start_conv
WAIT UNTIL write_ok = '1';
WAIT UNTIL rising_edge(clk);
-- Read out data using conv_addr
FOR i IN 0 TO IMG_SIZE*IMG_SIZE-1 LOOP
conv_addr <= std_logic_vector(to_unsigned(i, ADDR_WIDTH));
WAIT UNTIL rising_edge(clk);
END LOOP;
-- Simulate convolution done
done_conv <= '1';
WAIT UNTIL rising_edge(clk);
done_conv <= '0';
-- Wait and finish
WAIT;
END PROCESS;
END sim;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/21/2025
-- Design Name:
-- Module Name: tb_depacketizer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Testbench for depacketizer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY tb_depacketizer IS
END tb_depacketizer;
ARCHITECTURE Behavioral OF tb_depacketizer IS
COMPONENT depacketizer IS
GENERIC (
HEADER : INTEGER := 16#FF#;
FOOTER : INTEGER := 16#F1#
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC
);
END COMPONENT;
-- Constants
CONSTANT HEADER : INTEGER := 16#FF#;
CONSTANT FOOTER : INTEGER := 16#F1#;
-- Signals
SIGNAL clk : STD_LOGIC := '0';
SIGNAL aresetn : STD_LOGIC := '0';
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axis_tvalid : STD_LOGIC := '0';
SIGNAL s_axis_tready : STD_LOGIC;
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL m_axis_tvalid : STD_LOGIC;
SIGNAL m_axis_tready : STD_LOGIC := '1';
SIGNAL m_axis_tlast : STD_LOGIC;
-- Stimulus memory
TYPE mem_type IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mem : mem_type := (
0 => x"10",
1 => x"20",
2 => x"30",
3 => x"04",
4 => x"54",
5 => x"65",
6 => x"73",
7 => x"50"
);
SIGNAL tready_block_req : STD_LOGIC := '0';
BEGIN
-- Clock generation
clk <= NOT clk AFTER 5 ns;
-- Asynchronous tready block process
PROCESS (clk)
VARIABLE block_counter : INTEGER := 0;
VARIABLE tready_blocked : BOOLEAN := FALSE;
BEGIN
IF rising_edge(clk) THEN
IF tready_block_req = '1' AND NOT tready_blocked THEN
tready_blocked := TRUE;
block_counter := 0;
END IF;
IF tready_blocked THEN
IF block_counter < 9 THEN
m_axis_tready <= '0';
block_counter := block_counter + 1;
ELSE
m_axis_tready <= '1';
tready_blocked := FALSE;
block_counter := 0;
END IF;
ELSE
m_axis_tready <= '1';
END IF;
END IF;
END PROCESS;
-- DUT instantiation
uut: depacketizer
PORT MAP (
clk => clk,
aresetn => aresetn,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast
);
-- Stimulus process
PROCESS
BEGIN
-- Reset
aresetn <= '0';
WAIT FOR 20 ns;
aresetn <= '1';
WAIT UNTIL rising_edge(clk);
-- Start tready block asynchronously after 60 ns
WAIT FOR 60 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- Send 4 data words as a packet with Header and Footer
-- Header
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Data
FOR i IN 0 TO 3 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
-- Footer
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Wait a bit, then send another packet of 2 words with Header and Footer
WAIT FOR 50 ns;
-- Header
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Data
FOR i IN 4 TO 5 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
-- Footer
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Start another tready block asynchronously
WAIT FOR 40 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- Send packet of 3 words with Header and Footer
WAIT FOR 30 ns;
-- Header
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Data
FOR i IN 5 TO 7 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
-- Footer
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Send packet of 4 words without initial waiting, with Header and Footer
-- Header
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
-- Data
FOR i IN 2 TO 6 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
-- Footer
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
s_axis_tvalid <= '1';
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
WAIT;
END PROCESS;
END Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/16/2025 04:23:36 PM
-- Design Name:
-- Module Name: img_conv_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY img_conv_tb IS
-- Port ( );
END img_conv_tb;
ARCHITECTURE Behavioral OF img_conv_tb IS
COMPONENT img_conv IS
GENERIC (
LOG2_N_COLS : POSITIVE := 8;
LOG2_N_ROWS : POSITIVE := 8
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC;
conv_addr : OUT STD_LOGIC_VECTOR(LOG2_N_COLS + LOG2_N_ROWS - 1 DOWNTO 0);
conv_data : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
start_conv : IN STD_LOGIC;
done_conv : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT LOG2_N_COLS : POSITIVE := 2;
CONSTANT LOG2_N_ROWS : POSITIVE := 2;
TYPE mem_type IS ARRAY(0 TO (2 ** LOG2_N_COLS) * (2 ** LOG2_N_ROWS) - 1) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
-- Fill memory with more varied values
SIGNAL mem : mem_type := (
0 => "0000001",
1 => "0101010",
2 => "0011100",
3 => "1110001",
4 => "0001011",
5 => "0110110",
6 => "1001001",
7 => "1111111",
8 => "0000111",
9 => "0010010",
10 => "0100101",
11 => "0111000",
12 => "1001100",
13 => "1011011",
14 => "1100110",
15 => "1010101"
);
SIGNAL clk : STD_LOGIC := '0';
SIGNAL aresetn : STD_LOGIC := '0';
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL m_axis_tvalid : STD_LOGIC;
SIGNAL m_axis_tready : STD_LOGIC;
SIGNAL m_axis_tlast : STD_LOGIC;
SIGNAL conv_addr : STD_LOGIC_VECTOR(LOG2_N_COLS + LOG2_N_ROWS - 1 DOWNTO 0);
SIGNAL conv_data : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL start_conv : STD_LOGIC;
SIGNAL done_conv : STD_LOGIC;
SIGNAL tready_block_req : STD_LOGIC := '0';
BEGIN
-- m_axis_tready logic with blocking step
PROCESS (clk)
VARIABLE block_counter : INTEGER := 0;
VARIABLE tready_blocked : BOOLEAN := FALSE;
BEGIN
IF rising_edge(clk) THEN
IF tready_block_req = '1' AND NOT tready_blocked THEN
tready_blocked := TRUE;
block_counter := 0;
END IF;
IF tready_blocked THEN
IF block_counter < 19 THEN
m_axis_tready <= '0';
block_counter := block_counter + 1;
ELSE
m_axis_tready <= '1';
tready_blocked := FALSE;
block_counter := 0;
END IF;
ELSE
m_axis_tready <= '1';
END IF;
END IF;
END PROCESS;
clk <= NOT clk AFTER 5 ns;
PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
conv_data <= mem(to_integer(unsigned(conv_addr)));
END IF;
END PROCESS;
img_conv_inst : img_conv
GENERIC MAP(
LOG2_N_COLS => LOG2_N_COLS,
LOG2_N_ROWS => LOG2_N_ROWS
)
PORT MAP(
clk => clk,
aresetn => aresetn,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
conv_addr => conv_addr,
conv_data => conv_data,
start_conv => start_conv,
done_conv => done_conv
);
PROCESS
BEGIN
WAIT FOR 10 ns;
aresetn <= '1';
WAIT UNTIL rising_edge(clk);
start_conv <= '1';
WAIT UNTIL rising_edge(clk);
start_conv <= '0';
-- Wait some cycles, then request tready block for 10 cycles
WAIT FOR 200 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
WAIT FOR 300 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
WAIT FOR 200 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
WAIT;
END PROCESS;
END Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_led_blinker is
end entity;
architecture behavior of tb_led_blinker is
-- Constants
constant CLK_PERIOD_NS : time := 10 ns;
constant BLINK_PERIOD_MS : integer := 1000;
constant N_BLINKS : integer := 4;
-- DUT signals
signal clk : std_logic := '0';
signal aresetn : std_logic := '0';
signal start_blink : std_logic := '0';
signal led : std_logic;
begin
-- Clock process
clk_process : process
begin
while true loop
clk <= not clk;
wait for CLK_PERIOD_NS / 2;
end loop;
end process;
-- Instantiate DUT
uut: entity work.led_blinker
generic map (
CLK_PERIOD_NS => 10,
BLINK_PERIOD_MS => BLINK_PERIOD_MS,
N_BLINKS => N_BLINKS
)
port map (
clk => clk,
aresetn => aresetn,
start_blink => start_blink,
led => led
);
-- Stimulus process
stimulus : process
begin
-- Reset
aresetn <= '0';
wait for 50 ns;
aresetn <= '1';
wait for 50 ns;
-- Primo impulso di start_blink
start_blink <= '1';
wait for 10 ns;
start_blink <= '0';
-- Aspetta metà blinking, poi rilancia start_blink
wait for 3 sec;
-- Secondo impulso (durante blinking)
start_blink <= '1';
wait for 10 ns;
start_blink <= '0';
-- Aspetta che finisca tutto
wait for 10 sec;
-- Fine simulazione
assert false report "Test completed." severity failure;
end process;
end architecture;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/21/2025
-- Design Name:
-- Module Name: tb_packetizer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Testbench for packetizer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY tb_packetizer IS
END tb_packetizer;
ARCHITECTURE Behavioral OF tb_packetizer IS
COMPONENT packetizer IS
GENERIC (
HEADER : INTEGER := 16#FF#;
FOOTER : INTEGER := 16#F1#
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC
);
END COMPONENT;
SIGNAL clk : STD_LOGIC := '0';
SIGNAL aresetn : STD_LOGIC := '0';
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axis_tvalid : STD_LOGIC := '0';
SIGNAL s_axis_tready : STD_LOGIC;
SIGNAL s_axis_tlast : STD_LOGIC := '0';
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL m_axis_tvalid : STD_LOGIC;
SIGNAL m_axis_tready : STD_LOGIC := '1';
-- Stimulus memory
TYPE mem_type IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL mem : mem_type := (
0 => x"10",
1 => x"20",
2 => x"30",
3 => x"04",
4 => x"54",
5 => x"65",
6 => x"73",
7 => x"90"
);
SIGNAL tready_block_req : STD_LOGIC := '0';
BEGIN
-- Clock generation
clk <= NOT clk AFTER 5 ns;
-- Asynchronous tready block process
PROCESS (clk)
VARIABLE block_counter : INTEGER := 0;
VARIABLE tready_blocked : BOOLEAN := FALSE;
BEGIN
IF rising_edge(clk) THEN
IF tready_block_req = '1' AND NOT tready_blocked THEN
tready_blocked := TRUE;
block_counter := 0;
END IF;
IF tready_blocked THEN
IF block_counter < 9 THEN
m_axis_tready <= '0';
block_counter := block_counter + 1;
ELSE
m_axis_tready <= '1';
tready_blocked := FALSE;
block_counter := 0;
END IF;
ELSE
m_axis_tready <= '1';
END IF;
END IF;
END PROCESS;
-- DUT instantiation
uut: packetizer
PORT MAP (
clk => clk,
aresetn => aresetn,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready
);
-- Stimulus process
PROCESS
BEGIN
-- Reset
aresetn <= '0';
WAIT FOR 20 ns;
aresetn <= '1';
WAIT UNTIL rising_edge(clk);
-- Start tready block asynchronously after 60 ns
WAIT FOR 60 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- Send 4 data words as a packet
FOR i IN 0 TO 3 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
IF i = 3 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
-- Wait for handshake
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
s_axis_tlast <= '0';
-- Wait a bit, then send another packet of 1 words
WAIT FOR 50 ns;
FOR i IN 4 TO 4 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
IF i = 4 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
s_axis_tlast <= '0';
-- Start another tready block asynchronously
WAIT FOR 40 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- Send packet of 3 words
WAIT FOR 30 ns;
FOR i IN 5 TO 7 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
IF i = 7 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
s_axis_tlast <= '0';
-- Send packet of 4 words without initial waiting
FOR i IN 2 TO 6 LOOP
s_axis_tdata <= mem(i);
s_axis_tvalid <= '1';
IF i = 6 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
s_axis_tlast <= '0';
WAIT;
END PROCESS;
END Behavioral;

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-- Testbench for rgb2gray
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY rgb2gray_tb IS
END rgb2gray_tb;
ARCHITECTURE Behavioral OF rgb2gray_tb IS
-- Component Declaration
COMPONENT rgb2gray
PORT (
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC
);
END COMPONENT;
-- Signals
SIGNAL clk : STD_LOGIC := '0';
SIGNAL resetn : STD_LOGIC := '0';
SIGNAL m_axis_tvalid : STD_LOGIC;
SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL m_axis_tready : STD_LOGIC := '1';
SIGNAL m_axis_tlast : STD_LOGIC;
SIGNAL s_axis_tvalid : STD_LOGIC := '0';
SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axis_tready : STD_LOGIC;
SIGNAL s_axis_tlast : STD_LOGIC := '0';
-- Stimulus memory for RGB triplets (R, G, B)
TYPE rgb_mem_type IS ARRAY(0 TO 8, 0 TO 2) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rgb_mem : rgb_mem_type := (
(x"1A", x"2F", x"7C"),
(x"05", x"7F", x"3B"),
(x"4D", x"12", x"6E"),
(x"7E", x"01", x"23"),
(x"3C", x"55", x"7A"),
(x"2B", x"0F", x"6D"),
(x"7B", x"7D", x"7C"),
(x"6A", x"3E", x"27"),
(x"0C", x"5A", x"7F")
);
SIGNAL tready_block_req : STD_LOGIC := '0';
BEGIN
clk <= NOT clk AFTER 5 ns; -- Clock generation
-- Asynchronous tready block process (simulate downstream backpressure)
PROCESS (clk)
VARIABLE block_counter : INTEGER := 0;
VARIABLE tready_blocked : BOOLEAN := FALSE;
BEGIN
IF rising_edge(clk) THEN
IF tready_block_req = '1' AND NOT tready_blocked THEN
tready_blocked := TRUE;
block_counter := 0;
END IF;
IF tready_blocked THEN
IF block_counter < 6 THEN
m_axis_tready <= '0';
block_counter := block_counter + 1;
ELSE
m_axis_tready <= '1';
tready_blocked := FALSE;
block_counter := 0;
END IF;
ELSE
m_axis_tready <= '1';
END IF;
END IF;
END PROCESS;
-- Instantiate the Device Under Test (DUT)
DUT : rgb2gray
PORT MAP(
clk => clk,
resetn => resetn,
m_axis_tvalid => m_axis_tvalid,
m_axis_tdata => m_axis_tdata,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
s_axis_tvalid => s_axis_tvalid,
s_axis_tdata => s_axis_tdata,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast
);
-- Stimulus process
stimulus_process : PROCESS
BEGIN
-- Reset
resetn <= '0';
WAIT FOR 20 ns;
resetn <= '1';
WAIT UNTIL rising_edge(clk);
-- Start tready block asynchronously after 40 ns
WAIT FOR 40 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- Send 3 RGB pixels (9 bytes)
FOR i IN 0 TO 2 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
-- Assert tlast at the end of the first group (i=2, j=2)
IF (i = 2 AND j = 2) THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
-- Wait, then send 2 more RGB pixels
WAIT FOR 30 ns;
FOR i IN 3 TO 4 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
-- Assert tlast at the end of this group (i=4, j=2)
IF (i = 4 AND j = 2) THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
-- Start another tready block asynchronously
WAIT FOR 30 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- Send 2 more RGB pixels
WAIT FOR 20 ns;
FOR i IN 5 TO 6 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
-- Assert tlast at the end of this group (i=6, j=2)
IF (i = 6 AND j = 2) THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
-- Send last 2 RGB pixels
FOR i IN 7 TO 8 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
-- Assert tlast at the very end (i=8, j=2)
IF (i = 8 AND j = 2) THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
WAIT;
END PROCESS;
END Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
Library xpm;
use xpm.vcomponents.all;
entity bram_controller is
generic (
ADDR_WIDTH: POSITIVE :=16
);
port (
clk : in std_logic;
aresetn : in std_logic;
addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
dout: out std_logic_vector(7 downto 0);
din: in std_logic_vector(7 downto 0);
we: in std_logic
);
end entity bram_controller;
architecture rtl of bram_controller is
begin
-- xpm_memory_spram: Single Port RAM
-- Xilinx Parameterized Macro, version 2020.2
xpm_memory_spram_inst : xpm_memory_spram
generic map (
ADDR_WIDTH_A => ADDR_WIDTH, -- DECIMAL
AUTO_SLEEP_TIME => 0, -- DECIMAL
BYTE_WRITE_WIDTH_A => 8, -- DECIMAL
CASCADE_HEIGHT => 0, -- DECIMAL
ECC_MODE => "no_ecc", -- String
MEMORY_INIT_FILE => "none", -- String
MEMORY_INIT_PARAM => "0", -- String
MEMORY_OPTIMIZATION => "true", -- String
MEMORY_PRIMITIVE => "block", -- String
MEMORY_SIZE => (2**ADDR_WIDTH)*8,-- DECIMAL
MESSAGE_CONTROL => 0, -- DECIMAL
READ_DATA_WIDTH_A => 8, -- DECIMAL
READ_LATENCY_A => 1, -- DECIMAL
READ_RESET_VALUE_A => "0", -- String
RST_MODE_A => "SYNC", -- String
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
USE_MEM_INIT => 1, -- DECIMAL
WAKEUP_TIME => "disable_sleep", -- String
WRITE_DATA_WIDTH_A => 8, -- DECIMAL
WRITE_MODE_A => "read_first" -- String
)
port map (
dbiterra => open, -- 1-bit output: Status signal to indicate double bit error occurrence
-- on the data output of port A.
douta => dout, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
sbiterra => open, -- 1-bit output: Status signal to indicate single bit error occurrence
-- on the data output of port A.
addra => addr, -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
clka => clk, -- 1-bit input: Clock signal for port A.
dina => din, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
ena => '1', -- 1-bit input: Memory enable signal for port A. Must be high on clock
-- cycles when read or write operations are initiated. Pipelined
-- internally.
injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
regcea => '1', -- 1-bit input: Clock Enable for the last register stage on the output
-- data path.
rsta => (not aresetn), -- 1-bit input: Reset signal for the final port A output register
-- stage. Synchronously resets output port douta to the value specified
-- by parameter READ_RESET_VALUE_A.
sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature.
wea(0) => we -- WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
-- for port A input data port dina. 1 bit wide when word-wide writes
-- are used. In byte-wide write configurations, each bit controls the
-- writing one byte of dina to address addra. For example, to
-- synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
-- is 32, wea would be 4'b0010.
);
-- End of xpm_memory_spram_inst instantiation
end architecture;

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---------- DEFAULT LIBRARIES -------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------
ENTITY bram_writer IS
GENERIC (
ADDR_WIDTH : POSITIVE := 16;
IMG_SIZE : POSITIVE := 256 -- Image size (256x256)
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC;
conv_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
conv_data : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
start_conv : OUT STD_LOGIC;
done_conv : IN STD_LOGIC;
write_ok : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
underflow : OUT STD_LOGIC
);
END ENTITY bram_writer;
ARCHITECTURE rtl OF bram_writer IS
COMPONENT bram_controller IS
GENERIC (
ADDR_WIDTH : POSITIVE := 16
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
we : IN STD_LOGIC
);
END COMPONENT;
TYPE state_type IS (IDLE, RECEIVING, CHECK_DATA, CONVOLUTION);
SIGNAL state : state_type := IDLE;
SIGNAL s_axis_tready_int : STD_LOGIC := '0';
SIGNAL bram_data_out : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- BRAM data output
SIGNAL bram_data_in : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- BRAM data input
SIGNAL bram_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- BRAM address
SIGNAL bram_we : STD_LOGIC := '0'; -- Write enable signal for BRAM
SIGNAL wr_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- Write address for BRAM
SIGNAL overflow_flag : STD_LOGIC := '0'; -- Overflow flag for BRAM write
BEGIN
-- Instantiate BRAM controller
BRAM_CTRL : bram_controller
GENERIC MAP(
ADDR_WIDTH => ADDR_WIDTH
)
PORT MAP(
clk => clk,
aresetn => aresetn,
addr => bram_addr,
dout => bram_data_out,
din => bram_data_in,
we => bram_we
);
-- Assign AXIS ready signal
s_axis_tready <= s_axis_tready_int;
-- Output only the lower 7 bits of BRAM data
conv_data <= bram_data_out(6 DOWNTO 0);
-- Select BRAM address based on state
WITH state SELECT bram_addr <= conv_addr WHEN CONVOLUTION,
wr_addr WHEN OTHERS;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF aresetn = '0' THEN
-- Reset all signals and state
state <= IDLE;
s_axis_tready_int <= '0';
bram_we <= '0';
wr_addr <= (OTHERS => '0');
start_conv <= '0';
write_ok <= '0';
overflow <= '0';
underflow <= '0';
overflow_flag <= '0';
ELSE
-- Default assignments for each clock cycle
start_conv <= '0';
bram_we <= '0';
write_ok <= '0';
overflow <= '0';
underflow <= '0';
s_axis_tready_int <= '1';
-- State machine for data handling
CASE state IS
WHEN IDLE =>
-- Wait for valid input data to start writing
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
wr_addr <= (OTHERS => '0');
bram_we <= '1'; -- Enable write to BRAM
bram_data_in <= s_axis_tdata; -- Write data to BRAM
state <= RECEIVING;
END IF;
WHEN RECEIVING =>
-- Receiving data, increment write address
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-- Check for overflow: if address reaches max image size
IF unsigned(wr_addr) = (IMG_SIZE ** 2 - 1) THEN
overflow_flag <= '1';
END IF;
-- Increment write address and write data to BRAM
wr_addr <= STD_LOGIC_VECTOR(unsigned(wr_addr) + 1);
bram_we <= '1'; -- Enable write to BRAM
bram_data_in <= s_axis_tdata; -- Write data to BRAM
-- Check for last data signal
IF s_axis_tlast = '1' THEN
state <= CHECK_DATA;
END IF;
END IF;
WHEN CHECK_DATA =>
-- Check for overflow/underflow after data reception
IF overflow_flag = '1' THEN
overflow <= '1';
overflow_flag <= '0';
state <= IDLE;
ELSIF unsigned(wr_addr) < (IMG_SIZE ** 2 - 1) THEN
underflow <= '1';
state <= IDLE;
ELSE
-- Data reception complete, start convolution
write_ok <= '1';
s_axis_tready_int <= '0';
start_conv <= '1';
state <= CONVOLUTION;
END IF;
WHEN CONVOLUTION =>
-- Wait for convolution to finish
s_axis_tready_int <= '0';
IF done_conv = '1' THEN
state <= IDLE;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

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---------- DEFAULT LIBRARIES -------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------
ENTITY depacketizer IS
GENERIC (
HEADER : INTEGER := 16#FF#;
FOOTER : INTEGER := 16#F1#
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC
);
END ENTITY depacketizer;
ARCHITECTURE rtl OF depacketizer IS
TYPE state_type IS (WAITING_HEADER, RECEIVING, SEND);
SIGNAL state : state_type := WAITING_HEADER;
SIGNAL s_axis_tready_int : STD_LOGIC := '1';
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tlast_int : STD_LOGIC := '0';
SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_ready : STD_LOGIC := '0';
BEGIN
s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int;
m_axis_tdata <= m_axis_tdata_int;
m_axis_tlast <= m_axis_tlast_int;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF aresetn = '0' THEN
state <= WAITING_HEADER;
m_axis_tdata_int <= (OTHERS => '0');
m_axis_tlast_int <= '0';
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
data_buffer <= (OTHERS => '0');
data_ready <= '0';
ELSE
m_axis_tlast_int <= '0';
CASE state IS
WHEN WAITING_HEADER =>
s_axis_tready_int <= '1';
m_axis_tvalid_int <= '0';
data_ready <= '0';
-- Wait for header value to start receiving data
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)) THEN
state <= RECEIVING;
END IF;
END IF;
WHEN RECEIVING =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF data_ready = '1' THEN
m_axis_tdata_int <= data_buffer;
m_axis_tvalid_int <= '1';
-- Check for footer value to signal end of packet
IF s_axis_tdata = STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)) THEN
m_axis_tlast_int <= '1';
state <= WAITING_HEADER;
s_axis_tready_int <= '0';
data_ready <= '0';
ELSE
state <= SEND;
s_axis_tready_int <= '0';
END IF;
END IF;
data_buffer <= s_axis_tdata;
data_ready <= '1';
END IF;
WHEN SEND =>
IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';
state <= RECEIVING;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

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---------- DEFAULT LIBRARIES -------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;
------------------------------------
ENTITY divider_by_3 IS
GENERIC (
BIT_DEPTH : INTEGER := 7
);
PORT (
dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
);
END divider_by_3;
ARCHITECTURE Behavioral OF divider_by_3 IS
CONSTANT N : INTEGER := BIT_DEPTH + 3;
CONSTANT DIVISION_MULTIPLIER : INTEGER := INTEGER(round(real(2 ** N) / 3.0));
CONSTANT OFFSET : INTEGER := 2 ** (N - 1);
CONSTANT MULT_WIDTH : INTEGER := BIT_DEPTH + 1 + N;
SIGNAL mult_result : UNSIGNED(MULT_WIDTH - 1 DOWNTO 0);
SIGNAL sum_with_offset : UNSIGNED(MULT_WIDTH - 1 DOWNTO 0);
BEGIN
-- Multiplication without loss of bits
mult_result <= dividend * TO_UNSIGNED(DIVISION_MULTIPLIER, N - 1);
-- Addition with offset, no loss of bits
sum_with_offset <= mult_result + TO_UNSIGNED(OFFSET, MULT_WIDTH);
-- Extract rounded result
result <= sum_with_offset(MULT_WIDTH - 2 DOWNTO MULT_WIDTH - BIT_DEPTH -1);
END Behavioral;

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---------- DEFAULT LIBRARIES -------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------
ENTITY img_conv IS
GENERIC (
LOG2_N_COLS : POSITIVE := 8;
LOG2_N_ROWS : POSITIVE := 8
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC;
conv_addr : OUT STD_LOGIC_VECTOR(LOG2_N_COLS + LOG2_N_ROWS - 1 DOWNTO 0);
conv_data : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
start_conv : IN STD_LOGIC;
done_conv : OUT STD_LOGIC
);
END ENTITY img_conv;
ARCHITECTURE rtl OF img_conv IS
-- 3x3 convolution matrix (kernel)
TYPE conv_mat_type IS ARRAY(0 TO 2, 0 TO 2) OF INTEGER;
CONSTANT conv_mat : conv_mat_type := ((-1, -1, -1), (-1, 8, -1), (-1, -1, -1));
-- Offset arrays for kernel position relative to current pixel
TYPE offset_array IS ARRAY(0 TO 2) OF INTEGER;
CONSTANT offset : offset_array := (-1, 0, 1);
-- State machine for convolution process
TYPE state_type IS (IDLE, START_CONVOLUTING, CONVOLUTING, WAIT_READY);
SIGNAL state : state_type := IDLE;
-- Current column and row in the image
SIGNAL col : UNSIGNED(LOG2_N_COLS - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL row : UNSIGNED(LOG2_N_ROWS - 1 DOWNTO 0) := (OTHERS => '0');
-- Indices for kernel matrix position (previous, current, next)
SIGNAL col_mat_idx_prv : INTEGER := 0;
SIGNAL row_mat_idx_prv : INTEGER := 0;
SIGNAL col_mat_idx : INTEGER := 0;
SIGNAL row_mat_idx : INTEGER := 0;
SIGNAL col_mat_idx_nxt : INTEGER := 0;
SIGNAL row_mat_idx_nxt : INTEGER := 0;
-- Accumulators for convolution result
SIGNAL conv_data_out, conv_data_int, conv_data_mul : SIGNED(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tvalid_int : STD_LOGIC;
-- Control signals for data flow and pipelining
SIGNAL trigger, prepare_data, ready_data, send_data : STD_LOGIC := '0';
SIGNAL tlast : STD_LOGIC := '0';
SIGNAL save_data : STD_LOGIC := '0';
BEGIN
m_axis_tvalid <= m_axis_tvalid_int;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF aresetn = '0' THEN
-- Reset all signals and state
state <= IDLE;
col <= (OTHERS => '0');
row <= (OTHERS => '0');
col_mat_idx_nxt <= 0;
row_mat_idx_nxt <= 0;
col_mat_idx_prv <= 0;
row_mat_idx_prv <= 0;
col_mat_idx <= 0;
row_mat_idx <= 0;
conv_data_out <= (OTHERS => '0');
conv_data_int <= (OTHERS => '0');
conv_data_mul <= (OTHERS => '0');
m_axis_tvalid_int <= '0';
m_axis_tdata <= (OTHERS => '0');
m_axis_tlast <= '0';
done_conv <= '0';
trigger <= '0';
prepare_data <= '0';
ready_data <= '0';
send_data <= '0';
tlast <= '0';
save_data <= '0';
conv_addr <= (OTHERS => '0');
ELSE
-- Default values for signals at each clock
done_conv <= '0';
m_axis_tlast <= '0';
CASE state IS
WHEN IDLE =>
-- Wait for start_conv signal to begin convolution
done_conv <= '0';
m_axis_tlast <= '0';
m_axis_tvalid_int <= '0';
m_axis_tdata <= (OTHERS => '0');
conv_data_out <= (OTHERS => '0');
conv_data_int <= (OTHERS => '0');
conv_data_mul <= (OTHERS => '0');
trigger <= '0';
prepare_data <= '0';
ready_data <= '0';
send_data <= '0';
tlast <= '0';
save_data <= '0';
conv_addr <= (OTHERS => '0');
IF start_conv = '1' THEN
state <= START_CONVOLUTING;
-- Reset image pointers
row <= (OTHERS => '0');
col <= (OTHERS => '0');
-- Request the first pixel and set pointer to second pixel
row_mat_idx_prv <= 0;
col_mat_idx_prv <= 0;
row_mat_idx <= 1;
col_mat_idx <= 1;
row_mat_idx_nxt <= 1;
col_mat_idx_nxt <= 2;
conv_addr <= (OTHERS => '0');
conv_data_out <= (OTHERS => '0');
conv_data_int <= (OTHERS => '0');
conv_data_mul <= (OTHERS => '0');
trigger <= '0';
prepare_data <= '0';
ready_data <= '0';
send_data <= '0';
tlast <= '0';
save_data <= '0';
m_axis_tvalid_int <= '0';
m_axis_tdata <= (OTHERS => '0');
m_axis_tlast <= '0';
done_conv <= '0';
END IF;
WHEN START_CONVOLUTING =>
-- Start the convolution process or resume from the previous state
conv_addr <= STD_LOGIC_VECTOR(
TO_UNSIGNED(
(TO_INTEGER(col) + offset(col_mat_idx_nxt)) +
(TO_INTEGER(row) + offset(row_mat_idx_nxt)) * (2 ** LOG2_N_COLS),
conv_addr'length
)
);
state <= CONVOLUTING;
WHEN CONVOLUTING =>
-- Perform convolution: multiply input by kernel coefficient and accumulate
conv_addr <= STD_LOGIC_VECTOR(
TO_UNSIGNED(
(TO_INTEGER(col) + offset(col_mat_idx_nxt)) +
(TO_INTEGER(row) + offset(row_mat_idx_nxt)) * (2 ** LOG2_N_COLS),
conv_addr'length
)
);
conv_data_mul <= RESIZE(
SIGNED('0' & conv_data) * TO_SIGNED(conv_mat(col_mat_idx_prv, row_mat_idx_prv), 5),
conv_data_mul'length
);
IF ready_data = '1' THEN
conv_data_out <= conv_data_int + conv_data_mul;
conv_data_int <= (OTHERS => '0');
ELSE
conv_data_int <= conv_data_int + conv_data_mul;
END IF;
trigger <= '0';
WHEN WAIT_READY =>
-- Wait for m_axis_tready signal before sending data and continuing
IF m_axis_tready = '1' THEN
conv_addr <= STD_LOGIC_VECTOR(
TO_UNSIGNED(
(TO_INTEGER(col) + offset(col_mat_idx_nxt)) +
(TO_INTEGER(row) + offset(row_mat_idx_nxt)) * (2 ** LOG2_N_COLS),
conv_addr'length
)
);
save_data <= '0';
state <= CONVOLUTING;
END IF;
-- Save convolution result only once per WAIT_READY state
IF save_data = '0' THEN
conv_data_mul <= RESIZE(
SIGNED('0' & conv_data) * TO_SIGNED(conv_mat(col_mat_idx_prv, row_mat_idx_prv), 5),
conv_data_mul'length
);
IF ready_data = '1' THEN
conv_data_out <= conv_data_int + conv_data_mul;
conv_data_int <= (OTHERS => '0');
ELSE
conv_data_int <= conv_data_int + conv_data_mul;
END IF;
save_data <= '1';
END IF;
END CASE;
-- Output data - master
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
-- If output not ready, wait before continuing
IF m_axis_tready = '0' AND m_axis_tvalid_int = '1' THEN
state <= WAIT_READY;
END IF;
-- Send data when ready and output interface is available
IF send_data = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tvalid_int <= '1';
IF tlast = '1' THEN
state <= IDLE;
done_conv <= '1';
m_axis_tlast <= '1';
tlast <= '0';
END IF;
-- Clamp output to 0..127 range
IF conv_data_out < 0 THEN
m_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, m_axis_tdata'length));
ELSIF conv_data_out > 127 THEN
m_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(127, m_axis_tdata'length));
ELSE
m_axis_tdata <= STD_LOGIC_VECTOR(conv_data_out(7 DOWNTO 0));
END IF;
-- Reset accumulator and trigger
conv_data_out <= (OTHERS => '0');
send_data <= '0';
END IF;
-- Main kernel/image sweep logic
IF state = CONVOLUTING OR state = START_CONVOLUTING OR (state = WAIT_READY AND m_axis_tready = '1') THEN
-- Update kernel and image indices, handle zero padding and end conditions
IF col_mat_idx_nxt = 1 AND col = (2 ** LOG2_N_COLS - 1) THEN
IF row_mat_idx_nxt = 1 AND row = (2 ** LOG2_N_ROWS - 1) THEN
-- Last pixel and last kernel position: finish convolution
IF tlast = '0' THEN
trigger <= '1'; -- Send last data
tlast <= '1';
END IF;
ELSIF row_mat_idx_nxt = 2 THEN
-- End of kernel, move to next image row
col <= (OTHERS => '0');
row <= row + 1;
row_mat_idx_nxt <= 0;
col_mat_idx_nxt <= 1; -- new row adding padding
trigger <= '1'; -- Send data
ELSE
-- Move to next kernel row
row_mat_idx_nxt <= row_mat_idx_nxt + 1;
col_mat_idx_nxt <= 0;
END IF;
ELSIF col_mat_idx_nxt = 2 THEN
IF row_mat_idx_nxt = 1 AND row = (2 ** LOG2_N_ROWS - 1) THEN
-- End of kernel column at last image row, move to next image column
col <= col + 1;
row_mat_idx_nxt <= 0;
col_mat_idx_nxt <= 0;
trigger <= '1'; -- Send data
ELSIF row_mat_idx_nxt = 2 THEN
-- End of kernel column and row, move to next image column
col <= col + 1;
IF row = 0 THEN
row_mat_idx_nxt <= 1; -- first row adding padding
ELSE
row_mat_idx_nxt <= 0;
END IF;
col_mat_idx_nxt <= 0;
trigger <= '1'; -- Send data
ELSE
-- Move to next kernel column
IF col = 0 THEN
col_mat_idx_nxt <= 1; -- first column adding padding
ELSE
col_mat_idx_nxt <= 0;
END IF;
row_mat_idx_nxt <= row_mat_idx_nxt + 1;
END IF;
ELSE
-- Continue kernel sweep: increment kernel column index
col_mat_idx_nxt <= col_mat_idx_nxt + 1;
END IF;
-- Pipeline control for output data
prepare_data <= trigger;
ready_data <= prepare_data;
send_data <= ready_data;
-- Update previous and current kernel indices
row_mat_idx_prv <= row_mat_idx;
col_mat_idx_prv <= col_mat_idx;
row_mat_idx <= row_mat_idx_nxt;
col_mat_idx <= col_mat_idx_nxt;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

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---------- DEFAULT LIBRARIES -------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
------------------------------------
ENTITY led_blinker IS
GENERIC (
CLK_PERIOD_NS : POSITIVE := 10;
BLINK_PERIOD_MS : POSITIVE := 1000;
N_BLINKS : POSITIVE := 4
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
start_blink : IN STD_LOGIC;
led : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF led_blinker IS
-- Calculations for widths and maximum values
CONSTANT CLK_PER_MS : INTEGER := 1_000_000 / CLK_PERIOD_NS; -- Clock cycles per millisecond
CONSTANT MAX_COUNT : INTEGER := CLK_PER_MS * BLINK_PERIOD_MS; -- Counter max value for one blink period
CONSTANT CNT_WIDTH : INTEGER := INTEGER(ceil(log2(real(MAX_COUNT)))); -- Bit width for counter
CONSTANT BLINK_WIDTH : INTEGER := INTEGER(ceil(log2(real(N_BLINKS + 1)))); -- Bit width for blink counter
SIGNAL counter : unsigned(CNT_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- Main blink period counter
SIGNAL blink_cnt : unsigned(BLINK_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); -- Number of completed blinks
SIGNAL blinking : STD_LOGIC := '0'; -- Indicates if blinking is active
SIGNAL led_reg : STD_LOGIC := '0'; -- Register for LED output
SIGNAL start_prev : STD_LOGIC := '0'; -- Previous value of start_blink
SIGNAL start_edge : STD_LOGIC; -- Rising edge detector for start_blink
BEGIN
-- Output assignment
led <= led_reg;
-- Main process: handles blinking logic and state
PROCESS (clk, aresetn)
BEGIN
IF aresetn = '0' THEN
-- Asynchronous reset: clear all registers and outputs
counter <= (OTHERS => '0');
blink_cnt <= (OTHERS => '0');
blinking <= '0';
led_reg <= '0';
start_prev <= '0';
start_edge <= '0';
ELSIF rising_edge(clk) THEN
-- Detect rising edge on start_blink input
start_edge <= start_blink AND NOT start_prev;
start_prev <= start_blink;
IF blinking = '0' THEN
-- Idle state: wait for start_blink rising edge to begin blinking
IF start_edge = '1' THEN
blinking <= '1';
counter <= (OTHERS => '0');
blink_cnt <= (OTHERS => '0');
led_reg <= '1'; -- Start with LED ON
END IF;
ELSE -- blinking = '1'
-- Blinking state: count clock cycles for ON/OFF periods
IF counter = to_unsigned(MAX_COUNT - 1, counter'length) THEN
counter <= (OTHERS => '0');
led_reg <= NOT led_reg; -- Toggle LED state
IF led_reg = '1' THEN -- End of ON phase
blink_cnt <= blink_cnt + 1;
-- Check if required number of blinks is reached
IF blink_cnt + 1 = to_unsigned(N_BLINKS, blink_cnt'length) THEN
blinking <= '0'; -- Stop blinking
led_reg <= '0'; -- Ensure LED is OFF at end
END IF;
END IF;
ELSE
counter <= counter + 1; -- Increment counter
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

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---------- DEFAULT LIBRARIES -------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
------------------------------------
ENTITY packetizer IS
GENERIC (
HEADER : INTEGER := 16#FF#;
FOOTER : INTEGER := 16#F1#
);
PORT (
clk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC
);
END ENTITY packetizer;
ARCHITECTURE rtl OF packetizer IS
TYPE state_type IS (SENDING_HEADER, STREAMING, SENDING_FOOTER);
SIGNAL state : state_type := SENDING_HEADER;
SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_axis_tready_int : STD_LOGIC;
SIGNAL m_axis_tvalid_int : STD_LOGIC;
SIGNAL trigger : STD_LOGIC := '0'; -- Used to control when to send data
BEGIN
s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int;
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF aresetn = '0' THEN
state <= SENDING_HEADER;
data_buffer <= (OTHERS => '0');
m_axis_tdata <= (OTHERS => '0');
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
ELSE
-- Input data - slave
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
data_buffer <= s_axis_tdata;
END IF;
-- Clear valid flag when master interface is ready
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
-- Send data when triggered
IF trigger = '1' THEN
IF (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= data_buffer;
s_axis_tready_int <= '1'; -- Enable slave interface
trigger <= '0';
ELSE
s_axis_tready_int <= '0'; -- Block slave interface to avoid data loss
END IF;
END IF;
-- State machine for packetization
CASE state IS
WHEN SENDING_HEADER =>
s_axis_tready_int <= '1'; -- Enable slave interface
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); -- Send header
m_axis_tvalid_int <= '1';
s_axis_tready_int <= m_axis_tready;
IF s_axis_tlast = '1' THEN
s_axis_tready_int <= '0'; -- Block slave interface if last
state <= SENDING_FOOTER;
ELSE
state <= STREAMING;
END IF;
trigger <= '1';
END IF;
WHEN STREAMING =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
s_axis_tready_int <= m_axis_tready;
IF s_axis_tlast = '1' THEN
s_axis_tready_int <= '0'; -- Block slave interface if last
state <= SENDING_FOOTER;
END IF;
trigger <= '1';
END IF;
WHEN SENDING_FOOTER =>
IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
s_axis_tready_int <= '0'; -- Block slave interface
data_buffer <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); -- Send footer
m_axis_tvalid_int <= '1';
trigger <= '1';
state <= SENDING_HEADER;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

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---------- DEFAULT LIBRARIES -------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
------------------------------------
ENTITY rgb2gray IS
PORT (
clk : IN STD_LOGIC;
resetn : IN STD_LOGIC;
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tready : OUT STD_LOGIC;
s_axis_tlast : IN STD_LOGIC
);
END rgb2gray;
ARCHITECTURE Behavioral OF rgb2gray IS
COMPONENT divider_by_3
GENERIC (
BIT_DEPTH : INTEGER := 7
);
PORT (
dividend : IN UNSIGNED(BIT_DEPTH + 1 DOWNTO 0);
result : OUT UNSIGNED(BIT_DEPTH - 1 DOWNTO 0)
);
END COMPONENT;
TYPE state_type IS (IDLE, ACCUMULATE, WAIT_DIV, SEND);
SIGNAL state : state_type := IDLE;
SIGNAL sum : UNSIGNED(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL rgb_sum : UNSIGNED(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL gray : UNSIGNED(6 DOWNTO 0);
SIGNAL count : INTEGER RANGE 0 TO 2 := 0;
SIGNAL m_axis_tvalid_int : STD_LOGIC := '0';
SIGNAL m_axis_tdata_int : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axis_tlast_int : STD_LOGIC := '0';
SIGNAL s_axis_tready_int : STD_LOGIC := '1';
SIGNAL last_seen : STD_LOGIC := '0';
BEGIN
-- Connect internal signals to output ports
s_axis_tready <= s_axis_tready_int;
m_axis_tvalid <= m_axis_tvalid_int;
m_axis_tdata <= m_axis_tdata_int;
m_axis_tlast <= m_axis_tlast_int;
-- Divider instance: divides the sum of RGB by 3 to obtain grayscale value
DIVIDER : divider_by_3
GENERIC MAP(
BIT_DEPTH => 7
)
PORT MAP(
dividend => rgb_sum,
result => gray
);
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
IF resetn = '0' THEN
-- Asynchronous reset: initialize all signals and state
state <= IDLE;
sum <= (OTHERS => '0');
rgb_sum <= (OTHERS => '0');
count <= 0;
m_axis_tvalid_int <= '0';
m_axis_tdata_int <= (OTHERS => '0');
m_axis_tlast_int <= '0';
s_axis_tready_int <= '1';
last_seen <= '0';
ELSE
-- Default assignments for each clock cycle
m_axis_tlast_int <= '0';
CASE state IS
WHEN IDLE =>
-- Wait for the first valid input sample
m_axis_tdata_int <= (OTHERS => '0');
sum <= (OTHERS => '0');
count <= 0;
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= unsigned('0' & s_axis_tdata);
count <= 1;
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
state <= ACCUMULATE;
END IF;
WHEN ACCUMULATE =>
-- Accumulate the next two color components (expecting 3 total: R, G, B)
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
sum <= sum + unsigned(s_axis_tdata);
IF count = 2 THEN
rgb_sum <= sum + unsigned(s_axis_tdata);
s_axis_tready_int <= '0';
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
state <= WAIT_DIV;
ELSE
count <= count + 1;
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
END IF;
END IF;
WHEN WAIT_DIV =>
-- Now gray is valid (output from divider)
m_axis_tdata_int <= '0' & STD_LOGIC_VECTOR(gray);
m_axis_tvalid_int <= '1';
s_axis_tready_int <= '0';
IF last_seen = '1' THEN
m_axis_tlast_int <= '1';
last_seen <= '0';
END IF;
state <= SEND;
WHEN SEND =>
-- Hold the data until it is accepted by the downstream module
IF m_axis_tvalid_int = '1' AND m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '1';
state <= IDLE;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;

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import sys
import subprocess
def install_and_import(package, package_name=None):
if package_name is None:
package_name = package
import importlib
try:
importlib.import_module(package)
except ImportError:
subprocess.check_call([sys.executable, "-m", "pip", "install", package_name])
finally:
globals()[package] = importlib.import_module(package)
install_and_import("serial", "pyserial")
install_and_import("PIL", "pillow")
install_and_import("tqdm")
install_and_import("numpy")
install_and_import("scipy")
from serial import Serial
import serial.tools.list_ports
from tqdm import tqdm
from PIL import Image
from scipy.signal import convolve2d
import numpy as np
IMAGE_OF = r'C:\DESD\LAB2\test\test_of.png'
IMAGE_UF = r'C:\DESD\LAB2\test\test_uf.png'
IMAGE_NAME3 = r'C:\DESD\LAB2\test\test3.png'
IMAGE_NAME2 = r'C:\DESD\LAB2\test\test2.png'
IMAGE_NAME1 = r'C:\DESD\LAB2\test\test1.png'
IMAGE_DEPACK_PACK = r'C:\DESD\LAB2\test\test_depack_pack.png'
BASYS3_PID = 0x6010
BASYS3_VID = 0x0403
IMG_HEIGHT = 256
IMG_WIDTH = 256
dev = ""
for port in serial.tools.list_ports.comports():
if (port.vid == BASYS3_VID and port.pid == BASYS3_PID):
dev = port.device
if not dev:
raise RuntimeError("Basys 3 Not Found!")
test_n = int(input("Insert test number (1, 2, 3, 4 (overflow), 5 (underflow) or 6 (depack > pack only)): ").strip())
if test_n not in [1, 2, 3, 4, 5, 6]:
raise RuntimeError("Test number must be 1, 2, 3, 4 (overflow), 5 (underflow) or 6 (depack > pack only)")
dev = Serial(dev, 115200)
img = Image.open(IMAGE_NAME1 if test_n == 1 else IMAGE_NAME2 if test_n == 2 else IMAGE_NAME3 if test_n == 3 else IMAGE_OF if test_n == 4 else IMAGE_UF if test_n == 5 else IMAGE_DEPACK_PACK)
if img.mode != "RGB":
img = img.convert("RGB")
if test_n == 4:
print("Check for overflow (LED U16)")
elif test_n == 5:
print("Check for underflow (LED U19)")
IMG_WIDTH, IMG_HEIGHT = img.size # Get dimensions from the image
mat = np.asarray(img, dtype=np.uint8)
mat = mat[:, :, :3]
if mat.max() > 127:
mat = mat // 2
res = b''
if test_n == 6:
print("Check for depack > pack")
total_bytes = IMG_HEIGHT * IMG_WIDTH * 3
for idx in tqdm(range(total_bytes)):
i = idx // (IMG_WIDTH * 3)
j = (idx // 3) % IMG_WIDTH
k = idx % 3
dev.write(b'\xff')
dev.write(bytes([mat[i, j, k]]))
dev.write(b'\xf1')
dev.flush()
# Read 3 bytes: header, data, footer
resp = dev.read(3)
res += resp[1:2] # Only keep the data byte
res_img = np.frombuffer(res, dtype=np.uint8)
res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH, 3))
else:
buff = mat.tobytes()
mat_gray = np.round(np.sum(mat, axis=2) / 3).astype(np.uint8)
sim_img = convolve2d(mat_gray, [[-1, -1, -1], [-1, 8, -1], [-1, -1, -1]], mode="same")
sim_img[sim_img < 0] = 0
sim_img[sim_img > 127] = 127
sim_img = sim_img.astype(np.uint8)
dev.write(b'\xff')
for i in tqdm(range(IMG_HEIGHT)):
dev.write(buff[i * IMG_WIDTH * 3:(i + 1) * IMG_WIDTH * 3])
dev.write(b'\xf1')
dev.flush()
if test_n == 4 or test_n == 5:
exit()
else:
res = dev.read(IMG_HEIGHT * IMG_WIDTH + 2)
res_img = np.frombuffer(res[1:-1], dtype=np.uint8)
res_img = res_img.reshape((IMG_HEIGHT, IMG_WIDTH))
if (test_n == 6 and (res_img == mat).all()) or (res_img == sim_img).all():
print("Image Match!")
im = Image.fromarray(res_img)
im.show()
else:
print("Image Mismatch!")
# Only for BW images and not for test_n == 6
if test_n != 6:
# Compute absolute difference
diff = np.abs(res_img.astype(np.int16) - sim_img.astype(np.int16))
# Normalize difference to 0-255 for visualization
if diff.max() > 0:
diff_norm = (diff * 255 // diff.max()).astype(np.uint8)
else:
diff_norm = diff.astype(np.uint8)
# Create a binary mask: white where difference is not zero
mask = (diff != 0) * 255
mask = mask.astype(np.uint8)
# Prepare images for side-by-side visualization
im_res = Image.fromarray(res_img)
im_diff = Image.fromarray(diff_norm)
im_sim = Image.fromarray(sim_img)
# Convert all to RGB for concatenation
im_res_rgb = im_res.convert("RGB")
im_diff_rgb = im_diff.convert("RGB")
im_sim_rgb = im_sim.convert("RGB")
# Concatenate images horizontally
total_width = im_res_rgb.width + im_diff_rgb.width + im_sim_rgb.width
max_height = max(im_res_rgb.height, im_diff_rgb.height, im_sim_rgb.height)
combined = Image.new("RGB", (total_width, max_height))
combined.paste(im_res_rgb, (0, 0))
combined.paste(im_diff_rgb, (im_res_rgb.width, 0))
combined.paste(im_sim_rgb, (im_res_rgb.width + im_diff_rgb.width, 0))
combined.show(title="Result | Diff | Reference")

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/bram_writer_test/bram_writer_test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="db44c0b9410c4eb8a804a71d784cd439"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="40"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/bram_controller.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_writer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="bram_writer"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_bram_writer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_bram_writer_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_bram_writer"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_bram_writer_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_bram_writer_behav.wdb" id="1">
<top_modules>
<top_module name="tb_bram_writer" />
<top_module name="vcomponents" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="274601fs"></ZoomEndTime>
<Cursor1Time time="0fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="340"></NameColumnWidth>
<ValueColumnWidth column_width="155"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="21" />
<wvobject fp_name="/tb_bram_writer/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/aresetn" type="logic">
<obj_property name="ElementShortName">aresetn</obj_property>
<obj_property name="ObjectShortName">aresetn</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider36">
<obj_property name="label">AXI4</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tdata" type="array">
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tvalid" type="logic">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tready" type="logic">
<obj_property name="ElementShortName">s_axis_tready</obj_property>
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/s_axis_tlast" type="logic">
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider37">
<obj_property name="label">FSM</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/state" type="other">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider38">
<obj_property name="label">BRAM</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/bram_addr" type="array">
<obj_property name="ElementShortName">bram_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">bram_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/wr_addr" type="array">
<obj_property name="ElementShortName">wr_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">wr_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/bram_writer_inst/bram_we" type="logic">
<obj_property name="ElementShortName">bram_we</obj_property>
<obj_property name="ObjectShortName">bram_we</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/conv_addr" type="array">
<obj_property name="ElementShortName">conv_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">conv_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/conv_data" type="array">
<obj_property name="ElementShortName">conv_data[6:0]</obj_property>
<obj_property name="ObjectShortName">conv_data[6:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/start_conv" type="logic">
<obj_property name="ElementShortName">start_conv</obj_property>
<obj_property name="ObjectShortName">start_conv</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/done_conv" type="logic">
<obj_property name="ElementShortName">done_conv</obj_property>
<obj_property name="ObjectShortName">done_conv</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider39">
<obj_property name="label">Out status</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/write_ok" type="logic">
<obj_property name="ElementShortName">write_ok</obj_property>
<obj_property name="ObjectShortName">write_ok</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/overflow" type="logic">
<obj_property name="ElementShortName">overflow</obj_property>
<obj_property name="ObjectShortName">overflow</obj_property>
</wvobject>
<wvobject fp_name="/tb_bram_writer/underflow" type="logic">
<obj_property name="ElementShortName">underflow</obj_property>
<obj_property name="ObjectShortName">underflow</obj_property>
</wvobject>
</wave_config>

211
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/depacketizer_test/depacketizer_test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="7b9c995611dd4a3a8cd1a23f331045b5"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="29"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/depacketizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="depacketizer"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_depacketizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_depacketizer_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_depacketizer"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_depacketizer_behav.wcfg"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

86
LAB2/vivado/depacketizer_test/tb_depacketizer_behav.wcfg Normal file
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@@ -0,0 +1,86 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_depacketizer_behav.wdb" id="1">
<top_modules>
<top_module name="tb_depacketizer" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="1000001fs"></ZoomEndTime>
<Cursor1Time time="150033fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="248"></NameColumnWidth>
<ValueColumnWidth column_width="115"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="14" />
<wvobject fp_name="/tb_depacketizer/mem" type="array">
<obj_property name="ElementShortName">mem[0:7][7:0]</obj_property>
<obj_property name="ObjectShortName">mem[0:7][7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/aresetn" type="logic">
<obj_property name="ElementShortName">aresetn</obj_property>
<obj_property name="ObjectShortName">aresetn</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/uut/state" type="other">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/uut/data_buffer" type="array">
<obj_property name="ElementShortName">data_buffer[7:0]</obj_property>
<obj_property name="ObjectShortName">data_buffer[7:0]</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider19">
<obj_property name="label">s_axis</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/s_axis_tdata" type="array">
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/s_axis_tvalid" type="logic">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/s_axis_tready" type="logic">
<obj_property name="ElementShortName">s_axis_tready</obj_property>
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider20">
<obj_property name="label">m_axis</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/m_axis_tdata" type="array">
<obj_property name="ElementShortName">m_axis_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/m_axis_tvalid" type="logic">
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/m_axis_tready" type="logic">
<obj_property name="ElementShortName">m_axis_tready</obj_property>
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_depacketizer/m_axis_tlast" type="logic">
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
<obj_property name="CustomSignalColor">#0000FF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wave_config>

205
LAB2/vivado/img_conv_test/img_conv_test.xpr Normal file
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@@ -0,0 +1,205 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/img_conv_test/img_conv_test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ac254788b71e44ff92abc438d357ca04"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="150"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
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<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/img_conv.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="img_conv"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_img_conv.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="img_conv_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
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<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
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<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
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<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
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<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
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<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/16/2025 04:23:36 PM
-- Design Name:
-- Module Name: img_conv_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity img_conv_tb is
-- Port ( );
end img_conv_tb;
architecture Behavioral of img_conv_tb is
component img_conv is
generic(
LOG2_N_COLS: POSITIVE :=8;
LOG2_N_ROWS: POSITIVE :=8
);
port (
clk : in std_logic;
aresetn : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tlast : out std_logic;
conv_addr: out std_logic_vector(LOG2_N_COLS+LOG2_N_ROWS-1 downto 0);
conv_data: in std_logic_vector(6 downto 0);
start_conv: in std_logic;
done_conv: out std_logic
);
end component;
constant LOG2_N_COLS: POSITIVE :=2;
constant LOG2_N_ROWS: POSITIVE :=2;
type mem_type is array(0 to (2**LOG2_N_COLS)*(2**LOG2_N_ROWS)-1) of std_logic_vector(6 downto 0);
signal mem : mem_type := (0=>"0000001",others => (others => '0'));
signal clk : std_logic :='0';
signal aresetn : std_logic :='0';
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tlast : std_logic;
signal conv_addr: std_logic_vector(LOG2_N_COLS+LOG2_N_ROWS-1 downto 0);
signal conv_data: std_logic_vector(6 downto 0);
signal start_conv: std_logic;
signal done_conv: std_logic;
begin
m_axis_tready<='1';
clk <= not clk after 5 ns;
process (clk)
begin
if(rising_edge(clk)) then
conv_data<=mem(to_integer(unsigned(conv_addr)));
end if;
end process;
img_conv_inst: img_conv
generic map(
LOG2_N_COLS => LOG2_N_COLS,
LOG2_N_ROWS => LOG2_N_ROWS
)
port map(
clk => clk,
aresetn => aresetn,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
conv_addr => conv_addr,
conv_data => conv_data,
start_conv => start_conv,
done_conv => done_conv
);
process
begin
wait for 10 ns;
aresetn<='1';
wait until rising_edge(clk);
start_conv<='1';
wait until rising_edge(clk);
start_conv<='0';
wait;
end process;
end Behavioral;

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/lab2/lab2.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../ip"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="6"/>
<Option Name="WTModelSimExportSim" Val="6"/>
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<Option Name="WTVcsExportSim" Val="6"/>
<Option Name="WTRivieraExportSim" Val="6"/>
<Option Name="WTActivehdlExportSim" Val="6"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/packetizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PPRDIR/../../src/led_blinker.vhd">
<FileInfo>
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</FileInfo>
</File>
<File Path="$PPRDIR/../../src/img_conv.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</File>
<File Path="$PPRDIR/../../src/depacketizer.vhd">
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<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PPRDIR/../../src/bram_controller.vhd">
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<File Path="$PPRDIR/../../src/bram_writer.vhd">
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<File Path="$PPRDIR/../../src/divider_by_3.vhd">
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<Attr Name="UsedIn" Val="synthesis"/>
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</File>
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<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
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</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../../cons/pins.xdc">
<FileInfo>
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</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
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<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/img_conv_tb.vhd">
<FileInfo>
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</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="img_conv_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PPRDIR/../../lab2/lab2.srcs/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

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LAB2/vivado/loopback/loopback.xpr Normal file
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@@ -0,0 +1,421 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/loopback/loopback.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="66e226cf10b24331bf3e60250910330e"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
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211
LAB2/vivado/packetizer_test/packetizer_test.xpr Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/packetizer_test/packetizer_test.xpr">
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/packetizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="packetizer"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_packetizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_packetizer_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_packetizer"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_packetizer_behav.wcfg"/>
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</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
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<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
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<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

92
LAB2/vivado/packetizer_test/tb_packetizer_behav.wcfg Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="tb_packetizer_behav.wdb" id="1">
<top_modules>
<top_module name="tb_packetizer" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="421034fs"></ZoomStartTime>
<ZoomEndTime time="654835fs"></ZoomEndTime>
<Cursor1Time time="475000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="248"></NameColumnWidth>
<ValueColumnWidth column_width="119"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="15" />
<wvobject fp_name="/tb_packetizer/mem" type="array">
<obj_property name="ElementShortName">mem[0:7][7:0]</obj_property>
<obj_property name="ObjectShortName">mem[0:7][7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/clk" type="logic">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/aresetn" type="logic">
<obj_property name="ElementShortName">aresetn</obj_property>
<obj_property name="ObjectShortName">aresetn</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/uut/state" type="other">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
<obj_property name="CustomSignalColor">#00FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/uut/data_buffer" type="array">
<obj_property name="ElementShortName">data_buffer[7:0]</obj_property>
<obj_property name="ObjectShortName">data_buffer[7:0]</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider40">
<obj_property name="label">s_axis</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/s_axis_tdata" type="array">
<obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/s_axis_tvalid" type="logic">
<obj_property name="ElementShortName">s_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/s_axis_tready" type="logic">
<obj_property name="ElementShortName">s_axis_tready</obj_property>
<obj_property name="ObjectShortName">s_axis_tready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/s_axis_tlast" type="logic">
<obj_property name="ElementShortName">s_axis_tlast</obj_property>
<obj_property name="ObjectShortName">s_axis_tlast</obj_property>
<obj_property name="CustomSignalColor">#0000FF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="divider" fp_name="divider39">
<obj_property name="label">m_axis</obj_property>
<obj_property name="DisplayName">label</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/m_axis_tdata" type="array">
<obj_property name="ElementShortName">m_axis_tdata[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tdata[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/m_axis_tvalid" type="logic">
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/m_axis_tready" type="logic">
<obj_property name="ElementShortName">m_axis_tready</obj_property>
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject fp_name="/tb_packetizer/m_axis_tlast" type="logic">
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
<obj_property name="CustomSignalColor">#0000FF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
</wave_config>

211
LAB2/vivado/rgb2grey_test/rgb2grey_test.xpr Normal file
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@@ -0,0 +1,211 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/rgb2grey_test/rgb2grey_test.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2e783875aa14478a86d117fd6ef68faf"/>
<Option Name="Part" Val="xc7a35tcpg236-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="WTXSimLaunchSim" Val="106"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../src/divider_by_3.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../src/rgb2gray.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="rgb2gray"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../sim/tb_rgb2gray.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="rgb2gray_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

3
README.md
View File

@@ -26,7 +26,8 @@ The course focuses on:
- `src/`: VHDL source files - `src/`: VHDL source files
- `sim/`: Simulation files - `sim/`: Simulation files
- `cons/`: Constraint files - `cons/`: Constraint files
- `vivado/`: Vivado project files - `vivado/`: Vivado project files
- `test/`: Test files and programs
## 🚀 Getting Started ## 🚀 Getting Started

28
vhdl_ls.toml
View File

@@ -1,6 +1,3 @@
[server]
enable = true
[libraries] [libraries]
# Assign separate libraries for each project # Assign separate libraries for each project
lab0_lib.files = [ lab0_lib.files = [
@@ -13,25 +10,22 @@ lab1_lib.files = [
"LAB1/sim/**/*.vhd" "LAB1/sim/**/*.vhd"
] ]
# lab2_lib.files = [ lab2_lib.files = [
# "LAB2/src/**/*.vhd", "LAB2/src/*.vhd",
# "LAB2/sim/**/*.vhd" "LAB2/sim/**/*.vhd"
# ] ]
# lab3_lib.files = [ # lab3_lib.files = [
# "LAB3/src/**/*.vhd", # "LAB3/src/**/*.vhd",
# "LAB3/sim/**/*.vhd" # "LAB3/sim/**/*.vhd"
# ] # ]
[analyses] xpm.files = [
on_save = true "C:/Xilinx/Vivado/2020.2/data/ip/xpm/xpm_VCOMP.vhd"
on_open = true
[ghdl]
standard = "08"
library_path = [
"C:/Xilinx/Vivado/2020.2/data/vhdl/src"
] ]
xpm.is_third_party = true
[vhdl] unisim.files = [
standard = "2008" "C:/Xilinx/Vivado/2020.2/data/vhdl/src/unisims/**/*.vhd"
]
unisim.is_third_party = true