Add testbench for packetizer: implement behavioral testbench, configure simulation settings, and define stimulus for packetization process

LAB2/sim/tb_packetizer.vhd

@@ -0,0 +1,208 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 04/21/2025
+-- Design Name: 
+-- Module Name: tb_packetizer - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: Testbench for packetizer
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY tb_packetizer IS
+END tb_packetizer;
+
+ARCHITECTURE Behavioral OF tb_packetizer IS
+
+    COMPONENT packetizer IS
+        GENERIC (
+            HEADER : INTEGER := 16#FF#;
+            FOOTER : INTEGER := 16#F1#
+        );
+        PORT (
+            clk : IN STD_LOGIC;
+            aresetn : IN STD_LOGIC;
+
+            s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+            s_axis_tvalid : IN STD_LOGIC;
+            s_axis_tready : OUT STD_LOGIC;
+            s_axis_tlast : IN STD_LOGIC;
+
+            m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+            m_axis_tvalid : OUT STD_LOGIC;
+            m_axis_tready : IN STD_LOGIC
+        );
+    END COMPONENT;
+
+    SIGNAL clk : STD_LOGIC := '0';
+    SIGNAL aresetn : STD_LOGIC := '0';
+
+    SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL s_axis_tvalid : STD_LOGIC := '0';
+    SIGNAL s_axis_tready : STD_LOGIC;
+    SIGNAL s_axis_tlast : STD_LOGIC := '0';
+
+    SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
+    SIGNAL m_axis_tvalid : STD_LOGIC;
+    SIGNAL m_axis_tready : STD_LOGIC := '1';
+
+    -- Stimulus memory
+    TYPE mem_type IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
+    SIGNAL mem : mem_type := (
+        0 => x"10",
+        1 => x"20",
+        2 => x"30",
+        3 => x"4",
+        4 => x"54",
+        5 => x"65",
+        6 => x"73",
+        7 => x"90"
+    );
+
+    SIGNAL data_index : INTEGER := 0;
+
+    SIGNAL tready_block_req : STD_LOGIC := '0';
+
+BEGIN
+
+    -- Clock generation
+    clk <= NOT clk AFTER 5 ns;
+
+    -- Asynchronous tready block process
+    PROCESS (clk)
+        VARIABLE block_counter : INTEGER := 0;
+        VARIABLE tready_blocked : BOOLEAN := FALSE;
+    BEGIN
+        IF rising_edge(clk) THEN
+            IF tready_block_req = '1' AND NOT tready_blocked THEN
+                tready_blocked := TRUE;
+                block_counter := 0;
+            END IF;
+
+            IF tready_blocked THEN
+                IF block_counter < 9 THEN
+                    m_axis_tready <= '0';
+                    block_counter := block_counter + 1;
+                ELSE
+                    m_axis_tready <= '1';
+                    tready_blocked := FALSE;
+                    block_counter := 0;
+                END IF;
+            ELSE
+                m_axis_tready <= '1';
+            END IF;
+        END IF;
+    END PROCESS;
+
+    -- DUT instantiation
+    uut: packetizer
+        PORT MAP (
+            clk => clk,
+            aresetn => aresetn,
+
+            s_axis_tdata => s_axis_tdata,
+            s_axis_tvalid => s_axis_tvalid,
+            s_axis_tready => s_axis_tready,
+            s_axis_tlast => s_axis_tlast,
+
+            m_axis_tdata => m_axis_tdata,
+            m_axis_tvalid => m_axis_tvalid,
+            m_axis_tready => m_axis_tready
+        );
+
+    -- Stimulus process
+    PROCESS
+    BEGIN
+        -- Reset
+        aresetn <= '0';
+        WAIT FOR 20 ns;
+        aresetn <= '1';
+        WAIT UNTIL rising_edge(clk);
+
+        -- Start tready block asynchronously after 60 ns
+        WAIT FOR 60 ns;
+        tready_block_req <= '1';
+        WAIT UNTIL rising_edge(clk);
+        tready_block_req <= '0';
+
+        -- Send 4 data words as a packet
+        FOR i IN 0 TO 3 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            IF i = 3 THEN
+                s_axis_tlast <= '1';
+            ELSE
+                s_axis_tlast <= '0';
+            END IF;
+            -- Wait for handshake
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+        s_axis_tlast <= '0';
+
+        -- Wait a bit, then send another packet of 2 words
+        WAIT FOR 50 ns;
+        FOR i IN 4 TO 5 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            IF i = 5 THEN
+                s_axis_tlast <= '1';
+            ELSE
+                s_axis_tlast <= '0';
+            END IF;
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+        s_axis_tlast <= '0';
+
+        -- Start another tready block asynchronously
+        WAIT FOR 40 ns;
+        tready_block_req <= '1';
+        WAIT UNTIL rising_edge(clk);
+        tready_block_req <= '0';
+
+        -- Send packet of 3 words
+        WAIT FOR 30 ns;
+        FOR i IN 5 TO 7 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            IF i = 7 THEN
+                s_axis_tlast <= '1';
+            ELSE
+                s_axis_tlast <= '0';
+            END IF;
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+        s_axis_tlast <= '0';
+
+        -- Send packet of 4 words without initial waiting
+        FOR i IN 2 TO 6 LOOP
+            s_axis_tdata <= mem(i);
+            s_axis_tvalid <= '1';
+            IF i = 6 THEN
+                s_axis_tlast <= '1';
+            ELSE
+                s_axis_tlast <= '0';
+            END IF;
+            WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
+            s_axis_tvalid <= '0';
+        END LOOP;
+        s_axis_tlast <= '0';
+
+        WAIT;
+    END PROCESS;
+
+END Behavioral;

LAB2/src/packetizer.vhd

@@ -18,22 +18,21 @@ ENTITY packetizer IS
 
         m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         m_axis_tvalid : OUT STD_LOGIC;
-        m_axis_tready : IN STD_LOGIC;
-        m_axis_tlast : OUT STD_LOGIC
+        m_axis_tready : IN STD_LOGIC
     );
 END ENTITY packetizer;
 
 ARCHITECTURE rtl OF packetizer IS
 
-    TYPE state_type IS (IDLE, SENDING_HEADER, SENDING_DATA, SENDING_FOOTER);
-    SIGNAL state : state_type := IDLE;
+    TYPE state_type IS (SENDING_HEADER, STREAMING, SENDING_FOOTER);
+    SIGNAL state : state_type := SENDING_HEADER;
 
     SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
     SIGNAL s_axis_tready_int : STD_LOGIC;
     SIGNAL m_axis_tvalid_int : STD_LOGIC;
 
-    SIGNAL last_seen : STD_LOGIC := '0';
+    SIGNAL trigger : STD_LOGIC := '0';
 
 BEGIN
 
@@ -41,75 +40,22 @@ BEGIN
     m_axis_tvalid <= m_axis_tvalid_int;
 
     PROCESS (clk)
-        VARIABLE trigger : STD_LOGIC := '0';
     BEGIN
 
         IF rising_edge(clk) THEN
             IF aresetn = '0' THEN
+                state <= SENDING_HEADER;
 
                 data_buffer <= (OTHERS => '0');
 
+                m_axis_tdata <= (OTHERS => '0');
+                m_axis_tvalid_int <= '0';
+
                 s_axis_tready_int <= '0';
                 m_axis_tvalid_int <= '0';
-                m_axis_tlast <= '0';
 
             ELSE
 
-                m_axis_tlast <= '0';
-
-                IF m_axis_tready = '1' THEN
-                    m_axis_tvalid_int <= '0';
-                END IF;
-
-                CASE state IS
-                    WHEN IDLE =>
-                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            state <= SENDING_HEADER;
-                        END IF;
-
-                    WHEN SENDING_HEADER =>
-                        IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
-                            m_axis_tvalid_int <= '1';
-                            m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8));
-
-                            state <= SENDING_DATA;
-                        END IF;
-
-                    WHEN SENDING_DATA =>
-                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
-                            IF s_axis_tlast = '1' THEN
-                                last_seen <= '1';
-                            END IF;
-
-                            trigger := '1';
-                        END IF;
-
-                        IF last_seen = '1' THEN
-                            state <= SENDING_FOOTER;
-                            last_seen <= '0';
-
-                            trigger := '1';
-                        END IF;
-
-                    WHEN SENDING_FOOTER =>
-                        IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
-                            m_axis_tvalid_int <= '1';
-                            m_axis_tlast <= '1';
-                            m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8));
-
-                            state <= IDLE;
-                        END IF;
-
-                END CASE;
-
-                -- Output data - master
-                IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
-                    m_axis_tvalid_int <= '1';
-                    m_axis_tdata <= data_buffer;
-
-                    trigger := '0';
-                END IF;
-
                 -- Input data - slave
                 s_axis_tready_int <= m_axis_tready;
 
@@ -117,6 +63,52 @@ BEGIN
                     data_buffer <= s_axis_tdata;
                 END IF;
 
+                -- Output data - master
+                IF m_axis_tready = '1' THEN
+                    m_axis_tvalid_int <= '0';
+                END IF;
+
+                IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
+                    m_axis_tvalid_int <= '1';
+                    m_axis_tdata <= data_buffer;
+
+                    trigger <= '0';
+                END IF;
+
+                -- State machine for packetization
+                CASE state IS
+
+                    WHEN SENDING_HEADER =>
+                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
+                            m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); -- Prepare header
+                            m_axis_tvalid_int <= '1'; --Send header
+
+                            trigger <= '1';
+                            state <= STREAMING;
+                        END IF;
+
+                    WHEN STREAMING =>
+                        IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
+                            IF s_axis_tlast = '1' THEN
+                                s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
+                                state <= SENDING_FOOTER;
+                            END IF;
+
+                            trigger <= '1';
+                        END IF;
+
+                    WHEN SENDING_FOOTER =>
+                        IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
+                            s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
+                            
+                            data_buffer <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); -- Send footer
+                            m_axis_tvalid_int <= '1';
+
+                            trigger <= '1';
+                            state <= SENDING_HEADER;
+                        END IF;
+
+                END CASE;
             END IF;
         END IF;
 

LAB2/vivado/packetizer_test/packetizer_test.xpr

@@ -0,0 +1,214 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2020.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="54" Path="C:/DESD/LAB2/vivado/packetizer_test/packetizer_test.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="99ad126afeec4260ae1ad7f83b7defe8"/>
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirIES" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirIES" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../../Users/david/AppData/Roaming/Xilinx/Vivado/2020.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSABoardId" Val="basys3"/>
+    <Option Name="WTXSimLaunchSim" Val="41"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../src/packetizer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="packetizer"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <File Path="$PPRDIR/../../sim/tb_packetizer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/tb_packetizer_behav.wcfg">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="tb_packetizer"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/tb_packetizer_behav.wcfg"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="15">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2020"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>

LAB2/vivado/packetizer_test/tb_packetizer_behav.wcfg

@@ -0,0 +1,92 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="tb_packetizer_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="tb_packetizer" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="421034fs"></ZoomStartTime>
+      <ZoomEndTime time="654835fs"></ZoomEndTime>
+      <Cursor1Time time="475000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="248"></NameColumnWidth>
+      <ValueColumnWidth column_width="119"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="15" />
+   <wvobject fp_name="/tb_packetizer/mem" type="array">
+      <obj_property name="ElementShortName">mem[0:7][7:0]</obj_property>
+      <obj_property name="ObjectShortName">mem[0:7][7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/clk" type="logic">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/aresetn" type="logic">
+      <obj_property name="ElementShortName">aresetn</obj_property>
+      <obj_property name="ObjectShortName">aresetn</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/uut/state" type="other">
+      <obj_property name="ElementShortName">state</obj_property>
+      <obj_property name="ObjectShortName">state</obj_property>
+      <obj_property name="CustomSignalColor">#00FFFF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/uut/data_buffer" type="array">
+      <obj_property name="ElementShortName">data_buffer[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_buffer[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="divider" fp_name="divider40">
+      <obj_property name="label">s_axis</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/s_axis_tdata" type="array">
+      <obj_property name="ElementShortName">s_axis_tdata[7:0]</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tdata[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/s_axis_tvalid" type="logic">
+      <obj_property name="ElementShortName">s_axis_tvalid</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/s_axis_tready" type="logic">
+      <obj_property name="ElementShortName">s_axis_tready</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tready</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/s_axis_tlast" type="logic">
+      <obj_property name="ElementShortName">s_axis_tlast</obj_property>
+      <obj_property name="ObjectShortName">s_axis_tlast</obj_property>
+      <obj_property name="CustomSignalColor">#0000FF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject type="divider" fp_name="divider39">
+      <obj_property name="label">m_axis</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/m_axis_tdata" type="array">
+      <obj_property name="ElementShortName">m_axis_tdata[7:0]</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tdata[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/m_axis_tvalid" type="logic">
+      <obj_property name="ElementShortName">m_axis_tvalid</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/m_axis_tready" type="logic">
+      <obj_property name="ElementShortName">m_axis_tready</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tready</obj_property>
+      <obj_property name="CustomSignalColor">#FFD700</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+   <wvobject fp_name="/tb_packetizer/m_axis_tlast" type="logic">
+      <obj_property name="ElementShortName">m_axis_tlast</obj_property>
+      <obj_property name="ObjectShortName">m_axis_tlast</obj_property>
+      <obj_property name="CustomSignalColor">#0000FF</obj_property>
+      <obj_property name="UseCustomSignalColor">true</obj_property>
+   </wvobject>
+</wave_config>