Add testbench for packetizer: implement behavioral testbench, configure simulation settings, and define stimulus for packetization process

This commit is contained in:
2025-04-22 16:24:22 +02:00
parent 47fca59a97
commit e2bcbf7d31
4 changed files with 568 additions and 62 deletions

View File

@@ -18,22 +18,21 @@ ENTITY packetizer IS
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tlast : OUT STD_LOGIC
m_axis_tready : IN STD_LOGIC
);
END ENTITY packetizer;
ARCHITECTURE rtl OF packetizer IS
TYPE state_type IS (IDLE, SENDING_HEADER, SENDING_DATA, SENDING_FOOTER);
SIGNAL state : state_type := IDLE;
TYPE state_type IS (SENDING_HEADER, STREAMING, SENDING_FOOTER);
SIGNAL state : state_type := SENDING_HEADER;
SIGNAL data_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_axis_tready_int : STD_LOGIC;
SIGNAL m_axis_tvalid_int : STD_LOGIC;
SIGNAL last_seen : STD_LOGIC := '0';
SIGNAL trigger : STD_LOGIC := '0';
BEGIN
@@ -41,75 +40,22 @@ BEGIN
m_axis_tvalid <= m_axis_tvalid_int;
PROCESS (clk)
VARIABLE trigger : STD_LOGIC := '0';
BEGIN
IF rising_edge(clk) THEN
IF aresetn = '0' THEN
state <= SENDING_HEADER;
data_buffer <= (OTHERS => '0');
m_axis_tdata <= (OTHERS => '0');
m_axis_tvalid_int <= '0';
s_axis_tready_int <= '0';
m_axis_tvalid_int <= '0';
m_axis_tlast <= '0';
ELSE
m_axis_tlast <= '0';
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
CASE state IS
WHEN IDLE =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
state <= SENDING_HEADER;
END IF;
WHEN SENDING_HEADER =>
IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8));
state <= SENDING_DATA;
END IF;
WHEN SENDING_DATA =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF s_axis_tlast = '1' THEN
last_seen <= '1';
END IF;
trigger := '1';
END IF;
IF last_seen = '1' THEN
state <= SENDING_FOOTER;
last_seen <= '0';
trigger := '1';
END IF;
WHEN SENDING_FOOTER =>
IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
m_axis_tvalid_int <= '1';
m_axis_tlast <= '1';
m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8));
state <= IDLE;
END IF;
END CASE;
-- Output data - master
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= data_buffer;
trigger := '0';
END IF;
-- Input data - slave
s_axis_tready_int <= m_axis_tready;
@@ -117,6 +63,52 @@ BEGIN
data_buffer <= s_axis_tdata;
END IF;
-- Output data - master
IF m_axis_tready = '1' THEN
m_axis_tvalid_int <= '0';
END IF;
IF trigger = '1' AND (m_axis_tvalid_int = '0' OR m_axis_tready = '1') THEN
m_axis_tvalid_int <= '1';
m_axis_tdata <= data_buffer;
trigger <= '0';
END IF;
-- State machine for packetization
CASE state IS
WHEN SENDING_HEADER =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
m_axis_tdata <= STD_LOGIC_VECTOR(to_unsigned(HEADER, 8)); -- Prepare header
m_axis_tvalid_int <= '1'; --Send header
trigger <= '1';
state <= STREAMING;
END IF;
WHEN STREAMING =>
IF s_axis_tvalid = '1' AND s_axis_tready_int = '1' THEN
IF s_axis_tlast = '1' THEN
s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
state <= SENDING_FOOTER;
END IF;
trigger <= '1';
END IF;
WHEN SENDING_FOOTER =>
IF m_axis_tvalid_int = '0' OR m_axis_tready = '1' THEN
s_axis_tready_int <= '0'; -- Block the slave interface to avoid data loss
data_buffer <= STD_LOGIC_VECTOR(to_unsigned(FOOTER, 8)); -- Send footer
m_axis_tvalid_int <= '1';
trigger <= '1';
state <= SENDING_HEADER;
END IF;
END CASE;
END IF;
END IF;