PickleRick/DESD
1
0
Fork 0
Code Issues 2 Pull Requests Releases Activity

Refactor and clean up project files

Browse Source 
- Removed obsolete GraphML file `pak_depak.bda` and UI file `bd_c9b29a54.ui`.
- Updated `rgb2gray.vhd` to improve signal handling and state machine logic.
- Created new Vivado project files for `depacketizer_test`, including testbench configuration.
- Adjusted `pak_depak.xpr` to disable the FIFO module and set the top module correctly.
- Updated `rgb2grey_test.xpr` to modify simulation launch settings.
This commit is contained in:
Davide Cavagnola
2025-04-22 22:32:01 +02:00
parent e2bcbf7d31
commit f014f8c341
42 changed files with 747 additions and 19051 deletions
Download Patch File Download Diff File Expand all files Collapse all files

191
LAB2/sim/tb_rgb2gray.vhd
View File

@@ -40,13 +40,54 @@ ARCHITECTURE Behavioral OF rgb2gray_tb IS
SIGNAL s_axis_tready : STD_LOGIC;
SIGNAL s_axis_tlast : STD_LOGIC := '0';
-- Clock generation
-- Stimulus memory for RGB triplets (R, G, B)
TYPE rgb_mem_type IS ARRAY(0 TO 8, 0 TO 2) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rgb_mem : rgb_mem_type := (
(x"10", x"20", x"30"),
(x"40", x"50", x"60"),
(x"70", x"80", x"90"),
(x"A0", x"B0", x"C0"),
(x"D0", x"E0", x"F0"),
(x"01", x"02", x"03"),
(x"04", x"05", x"06"),
(x"07", x"08", x"09"),
(x"0A", x"0B", x"0C")
);
SIGNAL tready_block_req : STD_LOGIC := '0';
CONSTANT clk_period : TIME := 10 ns;
BEGIN
clk <= NOT clk AFTER clk_period / 2; -- Clock generation
-- Asynchronous tready block process (simulate downstream backpressure)
PROCESS (clk)
VARIABLE block_counter : INTEGER := 0;
VARIABLE tready_blocked : BOOLEAN := FALSE;
BEGIN
IF rising_edge(clk) THEN
IF tready_block_req = '1' AND NOT tready_blocked THEN
tready_blocked := TRUE;
block_counter := 0;
END IF;
IF tready_blocked THEN
IF block_counter < 6 THEN
m_axis_tready <= '0';
block_counter := block_counter + 1;
ELSE
m_axis_tready <= '1';
tready_blocked := FALSE;
block_counter := 0;
END IF;
ELSE
m_axis_tready <= '1';
END IF;
END IF;
END PROCESS;
-- Instantiate the Device Under Test (DUT)
DUT : rgb2gray
PORT MAP(
@@ -64,91 +105,91 @@ BEGIN
-- Stimulus process
stimulus_process : PROCESS
VARIABLE pixel_value : INTEGER := 1; -- Variable to increment pixel values
BEGIN
WAIT FOR 10 ns;
-- Reset
resetn <= '0';
WAIT FOR 20 ns;
resetn <= '1';
s_axis_tvalid <= '1';
WAIT UNTIL rising_edge(clk);
-- Send multiple RGB pixels with incrementing values
FOR i IN 0 TO 5 LOOP -- Send 10 pixels
-- R component
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- Start tready block asynchronously after 40 ns
WAIT FOR 40 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
-- G component
pixel_value := pixel_value + 5;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- B component
pixel_value := pixel_value + 1;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- Reset last signal
pixel_value := pixel_value + 1;
-- Send 3 RGB pixels (9 bytes)
FOR i IN 0 TO 2 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
IF i = 2 AND j = 2 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
-- Wait for handshake
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
m_axis_tready <= '0';
-- R component
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- G component
pixel_value := pixel_value + 5;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- B component
pixel_value := pixel_value + 1;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
FOR i IN 0 TO 3 LOOP -- Send 10 pixels
-- R component
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- G component
pixel_value := pixel_value + 5;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- B component
pixel_value := pixel_value + 1;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- Reset last signal
pixel_value := pixel_value + 1;
-- Wait, then send 2 more RGB pixels
WAIT FOR 30 ns;
FOR i IN 3 TO 4 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
IF i = 4 AND j = 2 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
m_axis_tready <= '1';
-- Start another tready block asynchronously
WAIT FOR 30 ns;
tready_block_req <= '1';
WAIT UNTIL rising_edge(clk);
tready_block_req <= '0';
FOR i IN 0 TO 3 LOOP -- Send 10 pixels
-- R component
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- G component
pixel_value := pixel_value + 5;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- B component
pixel_value := pixel_value + 1;
s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(pixel_value, 8));
WAIT FOR clk_period;
-- Reset last signal
pixel_value := pixel_value + 1;
-- Send 2 more RGB pixels
WAIT FOR 20 ns;
FOR i IN 5 TO 6 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
IF i = 6 AND j = 2 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
-- Deassert valid signal
s_axis_tlast <= '1'; -- Indicate end of pixel
s_axis_tvalid <= '0';
-- Send last 2 RGB pixels
FOR i IN 7 TO 8 LOOP
FOR j IN 0 TO 2 LOOP
s_axis_tdata <= rgb_mem(i, j);
s_axis_tvalid <= '1';
IF i = 8 AND j = 2 THEN
s_axis_tlast <= '1';
ELSE
s_axis_tlast <= '0';
END IF;
WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
s_axis_tvalid <= '0';
END LOOP;
END LOOP;
s_axis_tlast <= '0';
WAIT;
END PROCESS;