4 Commits

Author	SHA1	Message	Date
Davide	d156d1c944	Refactor project structure and update dependencies ... - Updated .gitignore to exclude virtual environment and additional test files. - Modified diligent_jstk.bd to reorganize interface nets for clarity. - Adjusted diligent_jstk.bda to correct node attributes and edges. - Revised diligent_jstk_wrapper.vhd to ensure proper port declarations. - Enhanced uart_viewer.py for improved image handling and serial connection checks. - Updated diligent_jstk.xpr and lab3.xpr for correct file paths and run configurations. - Added requirements.txt to specify project dependencies for Python packages.	2025-05-30 14:14:25 +02:00
Davide	5f30651763	Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.	2025-05-19 00:43:25 +02:00
Davide	1eb2181d1d	Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.	2025-05-17 13:29:40 +02:00
Cd16d	b11c65043f	Add AXI4-Stream UART IP and associated files ... - Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.	2025-05-12 18:16:58 +02:00