d65bb35afe
Update .gitignore, lab_3_wrapper.vhd, lab_3.bd, lab_3.bda, and digilent_jstk2.vhd for improved organization and functionality
Davide2025-05-30 14:32:33 +02:00
d156d1c944
Refactor project structure and update dependencies
Davide2025-05-30 14:14:25 +02:00
e21c00512f
Update clk to 100MHz
Davide2025-05-30 13:54:13 +02:00
1604a7afbc
Update SPI clock frequency in testbench and enhance comments in effect selector for clarity on joystick mode switching
Davide2025-05-28 19:28:14 +02:00
92cf8aa5ec
Update: - comments - new DELAY_CLK_CYCLES formula
Davide2025-05-28 18:06:01 +02:00
1b6bae5183
Refactor volume_saturator VHDL code for improved readability and structure; update project files for consistent path references and disable unused components in lab3 design.
Cd16d2025-05-19 16:24:36 +02:00
5f30651763
Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust node connections in diligent_jstk.bda, and modify delay parameter in digilent_jstk2.vhd for improved functionality and performance.
Davide2025-05-19 00:43:25 +02:00
6ab3f7bcde
Refactor LFO and design files: update LFO entity parameters, adjust signal handling, and modify project file paths for improved functionality and organization.
Davide2025-05-18 20:35:05 +02:00
be88f69202
Refactor LFO, all_pass_filter, and moving_average_filter: enhance output assignments, improve data handling, and streamline signal processing logic for better performance and maintainability.
Cd16d2025-05-18 00:36:30 +02:00
63aa004db9
Remove unused Vivado project zip file
Cd16d2025-05-17 22:04:44 +02:00
c5d238ec94
Refactor code structure for improved readability and maintainability
Davide2025-05-17 20:03:03 +02:00
cb57866a2e
Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization.
Davide2025-05-17 16:16:44 +02:00
1eb2181d1d
Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.
Davide2025-05-17 13:29:40 +02:00
8fd7db7575
Refactor diligent_jstk design files: update clock wizard paths, modify interface nets, enhance uart_viewer.py for real-time data visualization, and remove unused Vivado project zip file.
Davide2025-05-16 22:49:31 +02:00
460378cdaa
Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality
Cd16d2025-05-16 16:44:46 +02:00
55c5c84247
Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3.
Cd16d2025-05-16 16:43:45 +02:00
c3967c3124
Update VHDL and Python files for improved functionality and performance
Cd16d2025-05-15 16:46:09 +02:00
aa8d8f3c7c
Refactor design files for LAB3: update diligent_jstk and add testbench for digilent_jstk2
Cd16d2025-05-14 14:34:22 +02:00
b11c65043f
Add AXI4-Stream UART IP and associated files
Cd16d2025-05-12 18:16:58 +02:00
a4ec7ce43a
Add lab_3_wrapper VHDL file and update project files for LAB3
Cd16d2025-05-12 14:58:06 +02:00
3b3096d968
Merge pull request 'LAB3 - setup' (#2) from LAB3 into main
Davide Cavagnola2025-05-12 14:38:51 +02:00
c99622188d
Update design files for LAB3: reorganize components and adjust simulation settings
Cd16d2025-05-12 14:38:11 +02:00
60a8aa912d
Add initial design files and project configuration for LAB3
Cd16d2025-05-12 14:20:41 +02:00
835b4d0ab8
Refactor and update various components in LAB2 design
Davide2025-04-25 00:43:10 +02:00
5cabb20fdd
Refactor packetizer and depacketizer components; update test scripts and images
Davide2025-04-24 17:23:56 +02:00
a5b23940de
Refactor depacketizer: enhance state machine logic, improve signal handling, and streamline data processing for better functionality
Davide2025-04-24 13:07:26 +02:00
75fb66e531
Refactor rgb2gray and divider_by_3: update signal handling, enhance state management, and improve stimulus memory for better functionality and clarity
Davide2025-04-24 11:25:39 +02:00
5995a532f5
Refactor testbench for bram_writer: update description, increase image size, and enhance signal handling for improved simulation accuracy
Davide2025-04-23 01:49:46 +02:00
722b479811
Create design folder and update projects
Davide2025-04-22 22:56:28 +02:00
f014f8c341
Refactor and clean up project files
Davide2025-04-22 22:32:01 +02:00
e2bcbf7d31
Add testbench for packetizer: implement behavioral testbench, configure simulation settings, and define stimulus for packetization process
Davide2025-04-22 16:24:22 +02:00
47fca59a97
Refactor img_conv and tb_img_conv: enhance state management, improve signal handling, and add varied memory initialization for convolution processing
Davide2025-04-20 00:37:40 +02:00
a054085341
Add testbench for LED blinker, enhance bram_writer with state management, and update test script for overflow/underflow handling
Davide2025-04-17 22:55:49 +02:00
667632bfa3
Enhance bram_writer and testbench: add data handling for convolution, update state machine, and introduce new configuration files for simulation
Davide2025-04-17 21:29:02 +02:00
7ee12b37fe
Enhance bram_writer: add image size parameter, improve state machine for data handling, and refine signal management for better performance
Davide2025-04-17 19:21:15 +02:00
1d226709ac
Refactor bram_writer: streamline entity definition, remove unused signals, and enhance state management for improved clarity and functionality
Davide2025-04-17 17:25:21 +02:00
9bf8c21957
Refactor bram_writer and test script: improve code readability, update package installation method, and enhance image processing logic
Davide2025-04-17 01:24:18 +02:00
f363f09506
Implement finite state machine in bram_writer for improved data handling and convolution control
Davide2025-04-16 13:02:48 +02:00
b2d3060247
Refactor image processing components: update bit depth in rgb2gray and divider_by_3, enhance img_conv architecture, and adjust simulation settings
Davide2025-04-11 18:06:02 +02:00
c712b160cc
Refactor RGB to Grayscale conversion: update divider component and add testbench
Davide2025-04-11 13:00:46 +02:00
0d805b93b6
Refactor RGB to Grayscale Converter and Add Divider Component
Davide2025-04-11 01:50:19 +02:00
0912887822
TEMP Implement state machine in packetizer for improved packet handling
Davide2025-04-09 12:59:00 +02:00
1e84f090b7
Implement state machine in depacketizer for packet processing and add top auto-set option in project configuration
Davide2025-04-09 12:52:28 +02:00
360ae72198
Reorder reset, sys_clock and USB UART ports in lab_2_wrapper and update synthesis flow mode in lab_2.bd
Davide2025-04-09 11:40:21 +02:00
cd5d1b8a0c
Add new AXI4-Stream UART IP and update .gitignore for Lab2 files
Davide2025-03-31 18:35:29 +02:00
06afed32a3
Update README.md to include test files and programs section
Davide2025-03-29 00:58:19 +01:00
a5264642a6
Add new VHDL entities for image processing and update test scripts for Lab2
Davide2025-03-29 00:50:32 +01:00
58f8384507
Fix KittCarPWM to adjust BIT_LENGTH by reducing it by one
Davide2025-03-25 10:36:34 +01:00
8826072328
Refactor KittCarPWM to use dynamic bit lengths for PWM and timing counter
Davide2025-03-24 15:55:54 +01:00
Davide Cavagnola
Davide Cavagnola