2 Commits

Author	SHA1	Message	Date
Davide	1eb2181d1d	Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits.	2025-05-17 13:29:40 +02:00
Cd16d	b11c65043f	Add AXI4-Stream UART IP and associated files ... - Created board.xit for physical constraints related to UART interface. - Added vv_index.xml to define the AXI4-Stream UART IP with relevant metadata. - Implemented GUI for AXI4-Stream UART parameters in AXI4Stream_UART_v1_0.tcl and AXI4Stream_UART_v1_1.tcl. - Initialized Vivado project files for diligent_jstk and loopback_I2S designs, including synthesis and implementation settings. - Configured file sets and simulation options for both projects.	2025-05-12 18:16:58 +02:00