Commit Graph

8 Commits

Author SHA1 Message Date
c5d238ec94 Refactor code structure for improved readability and maintainability 2025-05-17 20:03:03 +02:00
cb57866a2e Refactor diligent_jstk design files: update interface nets in diligent_jstk.bd, adjust UART interface in uart_viewer.py for enhanced data handling, and modify digilent_jstk2.vhd to remove unnecessary initialization. 2025-05-17 16:16:44 +02:00
1eb2181d1d Update design files for diligent_jstk: change synthesis flow mode to Hierarchical, adjust XCI paths, and enhance UART viewer for real-time coordinate visualization with updated axis limits. 2025-05-17 13:29:40 +02:00
460378cdaa Update digilent_jstk2.vhd to clarify the required packet delay for SPI IP-Core functionality 2025-05-16 16:44:46 +02:00
55c5c84247 Refactor lab_3.bda to update node IDs and edge connections; modify digilent_jstk2.vhd to increase packet delay and adjust state machine; enhance uart_viewer.py for real-time coordinate visualization using matplotlib; update diligent_jstk.xpr simulation settings and remove unused file sets; add new Vivado project zip files for diligent_jstk and lab3. 2025-05-16 16:43:45 +02:00
c3967c3124 Update VHDL and Python files for improved functionality and performance
- Updated the date in the diligent_jstk_wrapper.vhd file.
- Modified the testbench (tb_digilent_jstk2.vhd) to ensure proper data transmission and added a delay to simulate real response time.
- Adjusted the digilent_jstk2.vhd file to refine the state machine logic for sending and receiving data, including a new IDLE state and improved handling of the SPI communication.
- Enhanced uart_viewer.py to automatically detect the Basys3 board's serial port, improving user experience and reducing configuration errors.
- Updated the Vivado project file (diligent_jstk.xpr) to reflect changes in simulation and synthesis settings, ensuring compatibility with the latest design updates.
2025-05-15 16:46:09 +02:00
aa8d8f3c7c Refactor design files for LAB3: update diligent_jstk and add testbench for digilent_jstk2 2025-05-14 14:34:22 +02:00
9c20fe7e7c Add initial implementations for various audio processing components
- Created LFO entity for low-frequency oscillation control.
- Added all_pass_filter entity for signal processing.
- Implemented balance_controller for audio balance adjustments.
- Developed debouncer to stabilize input signals.
- Introduced digilent_jstk2 for joystick data handling.
- Added edge_detector_toggle for edge detection functionality.
- Created effect_selector to manage audio effects based on joystick input.
- Implemented jstk_uart_bridge for communication between joystick and UART.
- Developed led_controller for LED management.
- Introduced led_level_controller for controlling multiple LEDs.
- Created moving_average_filter for smoothing input signals.
- Added moving_average_filter_en with enable functionality.
- Implemented mute_controller to handle mute functionality.
- Developed volume_controller for volume adjustments.
- Introduced volume_multiplier for scaling audio signals.
- Created volume_saturator to ensure audio signals stay within bounds.
2025-05-11 12:43:38 +02:00