LAB3/design/diligent_jstk/diligent_jstk.bd

@@ -5,7 +5,7 @@
       "device": "xc7a35tcpg236-1",
       "name": "diligent_jstk",
       "rev_ctrl_bd_flag": "RevCtrlBdOff",
-      "synth_flow_mode": "Hierarchical",
+      "synth_flow_mode": "None",
       "tool_version": "2020.2",
       "validated": "true"
     },
@@ -15,8 +15,8 @@
       "AXI4Stream_UART_0": "",
       "jstk_uart_bridge_0": "",
       "axi4stream_spi_master_0": "",
-      "digilent_jstk2_0": "",
+      "system_ila_0": "",
-      "system_ila_0": ""
+      "digilent_jstk2_0": ""
     },
     "interface_ports": {
       "usb_uart": {
@@ -338,6 +338,42 @@
           }
         }
       },
+      "system_ila_0": {
+        "vlnv": "xilinx.com:ip:system_ila:1.1",
+        "xci_name": "diligent_jstk_system_ila_0_0",
+        "xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
+        "inst_hier_path": "system_ila_0",
+        "parameters": {
+          "C_MON_TYPE": {
+            "value": "MIX"
+          },
+          "C_NUM_MONITOR_SLOTS": {
+            "value": "2"
+          },
+          "C_NUM_OF_PROBES": {
+            "value": "7"
+          },
+          "C_SLOT": {
+            "value": "1"
+          },
+          "C_SLOT_0_INTF_TYPE": {
+            "value": "xilinx.com:interface:axis_rtl:1.0"
+          },
+          "C_SLOT_1_INTF_TYPE": {
+            "value": "xilinx.com:interface:axis_rtl:1.0"
+          }
+        },
+        "interface_ports": {
+          "SLOT_0_AXIS": {
+            "mode": "Monitor",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
+          },
+          "SLOT_1_AXIS": {
+            "mode": "Monitor",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
+          }
+        }
+      },
       "digilent_jstk2_0": {
         "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
         "xci_name": "diligent_jstk_digilent_jstk2_0_0",
@@ -552,39 +588,21 @@
             "right": "0"
           }
         }
-      },
-      "system_ila_0": {
-        "vlnv": "xilinx.com:ip:system_ila:1.1",
-        "xci_name": "diligent_jstk_system_ila_0_0",
-        "xci_path": "ip\\diligent_jstk_system_ila_0_0\\diligent_jstk_system_ila_0_0.xci",
-        "inst_hier_path": "system_ila_0",
-        "parameters": {
-          "C_NUM_MONITOR_SLOTS": {
-            "value": "2"
-          },
-          "C_SLOT": {
-            "value": "1"
-          },
-          "C_SLOT_0_INTF_TYPE": {
-            "value": "xilinx.com:interface:axis_rtl:1.0"
-          },
-          "C_SLOT_1_INTF_TYPE": {
-            "value": "xilinx.com:interface:axis_rtl:1.0"
-          }
-        },
-        "interface_ports": {
-          "SLOT_0_AXIS": {
-            "mode": "Monitor",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
-          },
-          "SLOT_1_AXIS": {
-            "mode": "Monitor",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0"
-          }
-        }
       }
     },
     "interface_nets": {
+      "axi4stream_spi_master_0_SPI_M": {
+        "interface_ports": [
+          "SPI_M_0",
+          "axi4stream_spi_master_0/SPI_M"
+        ]
+      },
+      "AXI4Stream_UART_0_UART": {
+        "interface_ports": [
+          "usb_uart",
+          "AXI4Stream_UART_0/UART"
+        ]
+      },
       "jstk_uart_bridge_0_m_axis": {
         "interface_ports": [
           "AXI4Stream_UART_0/S00_AXIS_TX",
@@ -597,13 +615,6 @@
           "jstk_uart_bridge_0/s_axis"
         ]
       },
-      "digilent_jstk2_0_m_axis": {
-        "interface_ports": [
-          "digilent_jstk2_0/m_axis",
-          "axi4stream_spi_master_0/S_AXIS",
-          "system_ila_0/SLOT_0_AXIS"
-        ]
-      },
       "axi4stream_spi_master_0_M_AXIS": {
         "interface_ports": [
           "axi4stream_spi_master_0/M_AXIS",
@@ -611,16 +622,11 @@
           "system_ila_0/SLOT_1_AXIS"
         ]
       },
-      "AXI4Stream_UART_0_UART": {
+      "digilent_jstk2_0_m_axis": {
         "interface_ports": [
-          "usb_uart",
+          "digilent_jstk2_0/m_axis",
-          "AXI4Stream_UART_0/UART"
+          "axi4stream_spi_master_0/S_AXIS",
-        ]
+          "system_ila_0/SLOT_0_AXIS"
-      },
-      "axi4stream_spi_master_0_SPI_M": {
-        "interface_ports": [
-          "SPI_M_0",
-          "axi4stream_spi_master_0/SPI_M"
         ]
       }
     },
@@ -653,49 +659,56 @@
           "AXI4Stream_UART_0/m00_axis_rx_aclk",
           "jstk_uart_bridge_0/aclk",
           "AXI4Stream_UART_0/s00_axis_tx_aclk",
-          "digilent_jstk2_0/aclk",
+          "system_ila_0/clk",
-          "system_ila_0/clk"
+          "digilent_jstk2_0/aclk"
         ]
       },
       "digilent_jstk2_0_btn_trigger": {
         "ports": [
           "digilent_jstk2_0/btn_trigger",
-          "jstk_uart_bridge_0/btn_trigger"
+          "jstk_uart_bridge_0/btn_trigger",
+          "system_ila_0/probe6"
         ]
       },
       "digilent_jstk2_0_btn_jstk": {
         "ports": [
           "digilent_jstk2_0/btn_jstk",
-          "jstk_uart_bridge_0/btn_jstk"
+          "jstk_uart_bridge_0/btn_jstk",
+          "system_ila_0/probe5"
         ]
       },
       "digilent_jstk2_0_jstk_y": {
         "ports": [
           "digilent_jstk2_0/jstk_y",
-          "jstk_uart_bridge_0/jstk_y"
+          "jstk_uart_bridge_0/jstk_y",
+          "system_ila_0/probe4"
         ]
       },
       "digilent_jstk2_0_jstk_x": {
         "ports": [
           "digilent_jstk2_0/jstk_x",
-          "jstk_uart_bridge_0/jstk_x"
+          "jstk_uart_bridge_0/jstk_x",
+          "system_ila_0/probe3"
         ]
       },
       "jstk_uart_bridge_0_led_r": {
         "ports": [
           "jstk_uart_bridge_0/led_r",
+          "system_ila_0/probe0",
           "digilent_jstk2_0/led_r"
         ]
       },
       "jstk_uart_bridge_0_led_g": {
         "ports": [
           "jstk_uart_bridge_0/led_g",
+          "system_ila_0/probe1",
           "digilent_jstk2_0/led_g"
         ]
       },
       "jstk_uart_bridge_0_led_b": {
         "ports": [
           "jstk_uart_bridge_0/led_b",
+          "system_ila_0/probe2",
           "digilent_jstk2_0/led_b"
         ]
       },
@@ -706,8 +719,8 @@
           "jstk_uart_bridge_0/aresetn",
           "AXI4Stream_UART_0/s00_axis_tx_aresetn",
           "axi4stream_spi_master_0/aresetn",
-          "digilent_jstk2_0/aresetn",
+          "system_ila_0/resetn",
-          "system_ila_0/resetn"
+          "digilent_jstk2_0/aresetn"
         ]
       },
       "proc_sys_reset_0_peripheral_reset": {

LAB3/design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd

@@ -1,7 +1,7 @@
 --Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------
 --Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020
---Date        : Thu May 15 16:34:14 2025
+--Date        : Fri May 16 16:28:03 2025
 --Host        : Davide-Samsung running 64-bit major release  (build 9200)
 --Command     : generate_target diligent_jstk_wrapper.bd
 --Design      : diligent_jstk_wrapper

LAB3/design/lab_3/lab_3.bd

@@ -6,14 +6,12 @@
       "name": "lab_3",
       "rev_ctrl_bd_flag": "RevCtrlBdOff",
       "synth_flow_mode": "None",
-      "tool_version": "2020.2",
+      "tool_version": "2020.2"
-      "validated": "true"
     },
     "design_tree": {
       "clk_wiz_0": "",
       "proc_sys_reset_0": "",
       "proc_sys_reset_1": "",
-      "digilent_jstk2_0": "",
       "edge_detector_toggle_0": "",
       "edge_detector_toggle_1": "",
       "debouncer_0": "",
@@ -27,7 +25,8 @@
       "led_level_controller_0": "",
       "mute_controller_0": "",
       "axi4stream_spi_master_0": "",
-      "axis_dual_i2s_0": ""
+      "axis_dual_i2s_0": "",
+      "digilent_jstk2_0": ""
     },
     "interface_ports": {
       "SPI_M_0": {
@@ -40,21 +39,9 @@
         "type": "clk",
         "direction": "I",
         "parameters": {
-          "CLK_DOMAIN": {
-            "value": "lab_3_sys_clock",
-            "value_src": "default"
-          },
           "FREQ_HZ": {
             "value": "100000000"
           },
-          "FREQ_TOLERANCE_HZ": {
-            "value": "0",
-            "value_src": "default"
-          },
-          "INSERT_VIP": {
-            "value": "0",
-            "value_src": "default"
-          },
           "PHASE": {
             "value": "0.000"
           }
@@ -64,10 +51,6 @@
         "type": "rst",
         "direction": "I",
         "parameters": {
-          "INSERT_VIP": {
-            "value": "0",
-            "value_src": "default"
-          },
           "POLARITY": {
             "value": "ACTIVE_HIGH"
           }
@@ -178,221 +161,6 @@
         "xci_path": "ip\\lab_3_proc_sys_reset_1_0\\lab_3_proc_sys_reset_1_0.xci",
         "inst_hier_path": "proc_sys_reset_1"
       },
-      "digilent_jstk2_0": {
-        "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
-        "xci_name": "lab_3_digilent_jstk2_0_0",
-        "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
-        "inst_hier_path": "digilent_jstk2_0",
-        "parameters": {
-          "CLKFREQ": {
-            "value": "215000000"
-          }
-        },
-        "reference_info": {
-          "ref_type": "hdl",
-          "ref_name": "digilent_jstk2",
-          "boundary_crc": "0x0"
-        },
-        "interface_ports": {
-          "m_axis": {
-            "mode": "Master",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "m_axis_tdata",
-                "direction": "O",
-                "left": "7",
-                "right": "0"
-              },
-              "TVALID": {
-                "physical_name": "m_axis_tvalid",
-                "direction": "O"
-              },
-              "TREADY": {
-                "physical_name": "m_axis_tready",
-                "direction": "I"
-              }
-            }
-          },
-          "s_axis": {
-            "mode": "Slave",
-            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
-            "parameters": {
-              "TDATA_NUM_BYTES": {
-                "value": "1",
-                "value_src": "constant"
-              },
-              "TDEST_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TID_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "TUSER_WIDTH": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TREADY": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TSTRB": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TKEEP": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "HAS_TLAST": {
-                "value": "0",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            },
-            "port_maps": {
-              "TDATA": {
-                "physical_name": "s_axis_tdata",
-                "direction": "I",
-                "left": "7",
-                "right": "0"
-              },
-              "TVALID": {
-                "physical_name": "s_axis_tvalid",
-                "direction": "I"
-              }
-            }
-          }
-        },
-        "ports": {
-          "aclk": {
-            "type": "clk",
-            "direction": "I",
-            "parameters": {
-              "ASSOCIATED_BUSIF": {
-                "value": "m_axis:s_axis",
-                "value_src": "constant"
-              },
-              "ASSOCIATED_RESET": {
-                "value": "aresetn",
-                "value_src": "constant"
-              },
-              "FREQ_HZ": {
-                "value": "100000000",
-                "value_src": "ip_prop"
-              },
-              "PHASE": {
-                "value": "0.0",
-                "value_src": "ip_prop"
-              },
-              "CLK_DOMAIN": {
-                "value": "/clk_wiz_0_clk_out1",
-                "value_src": "ip_prop"
-              }
-            }
-          },
-          "aresetn": {
-            "type": "rst",
-            "direction": "I",
-            "parameters": {
-              "POLARITY": {
-                "value": "ACTIVE_LOW",
-                "value_src": "constant"
-              }
-            }
-          },
-          "jstk_x": {
-            "direction": "O",
-            "left": "9",
-            "right": "0"
-          },
-          "jstk_y": {
-            "direction": "O",
-            "left": "9",
-            "right": "0"
-          },
-          "btn_jstk": {
-            "direction": "O"
-          },
-          "btn_trigger": {
-            "direction": "O"
-          },
-          "led_r": {
-            "direction": "I",
-            "left": "7",
-            "right": "0"
-          },
-          "led_g": {
-            "direction": "I",
-            "left": "7",
-            "right": "0"
-          },
-          "led_b": {
-            "direction": "I",
-            "left": "7",
-            "right": "0"
-          }
-        }
-      },
       "edge_detector_toggle_0": {
         "vlnv": "xilinx.com:module_ref:edge_detector_toggle:1.0",
         "xci_name": "lab_3_edge_detector_toggle_0_0",
@@ -1803,6 +1571,185 @@
         "xci_name": "lab_3_axis_dual_i2s_0_0",
         "xci_path": "ip\\lab_3_axis_dual_i2s_0_0\\lab_3_axis_dual_i2s_0_0.xci",
         "inst_hier_path": "axis_dual_i2s_0"
+      },
+      "digilent_jstk2_0": {
+        "vlnv": "xilinx.com:module_ref:digilent_jstk2:1.0",
+        "xci_name": "lab_3_digilent_jstk2_0_0",
+        "xci_path": "ip\\lab_3_digilent_jstk2_0_0\\lab_3_digilent_jstk2_0_0.xci",
+        "inst_hier_path": "digilent_jstk2_0",
+        "parameters": {
+          "CLKFREQ": {
+            "value": "215000000"
+          }
+        },
+        "reference_info": {
+          "ref_type": "hdl",
+          "ref_name": "digilent_jstk2",
+          "boundary_crc": "0x0"
+        },
+        "interface_ports": {
+          "m_axis": {
+            "mode": "Master",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+            "parameters": {
+              "TDATA_NUM_BYTES": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "TDEST_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TID_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TUSER_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TREADY": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "HAS_TSTRB": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TKEEP": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TLAST": {
+                "value": "0",
+                "value_src": "constant"
+              }
+            },
+            "port_maps": {
+              "TDATA": {
+                "physical_name": "m_axis_tdata",
+                "direction": "O",
+                "left": "7",
+                "right": "0"
+              },
+              "TVALID": {
+                "physical_name": "m_axis_tvalid",
+                "direction": "O"
+              },
+              "TREADY": {
+                "physical_name": "m_axis_tready",
+                "direction": "I"
+              }
+            }
+          },
+          "s_axis": {
+            "mode": "Slave",
+            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
+            "parameters": {
+              "TDATA_NUM_BYTES": {
+                "value": "1",
+                "value_src": "constant"
+              },
+              "TDEST_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TID_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "TUSER_WIDTH": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TREADY": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TSTRB": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TKEEP": {
+                "value": "0",
+                "value_src": "constant"
+              },
+              "HAS_TLAST": {
+                "value": "0",
+                "value_src": "constant"
+              }
+            },
+            "port_maps": {
+              "TDATA": {
+                "physical_name": "s_axis_tdata",
+                "direction": "I",
+                "left": "7",
+                "right": "0"
+              },
+              "TVALID": {
+                "physical_name": "s_axis_tvalid",
+                "direction": "I"
+              }
+            }
+          }
+        },
+        "ports": {
+          "aclk": {
+            "type": "clk",
+            "direction": "I",
+            "parameters": {
+              "ASSOCIATED_BUSIF": {
+                "value": "m_axis:s_axis",
+                "value_src": "constant"
+              },
+              "ASSOCIATED_RESET": {
+                "value": "aresetn",
+                "value_src": "constant"
+              }
+            }
+          },
+          "aresetn": {
+            "type": "rst",
+            "direction": "I",
+            "parameters": {
+              "POLARITY": {
+                "value": "ACTIVE_LOW",
+                "value_src": "constant"
+              }
+            }
+          },
+          "jstk_x": {
+            "direction": "O",
+            "left": "9",
+            "right": "0"
+          },
+          "jstk_y": {
+            "direction": "O",
+            "left": "9",
+            "right": "0"
+          },
+          "btn_jstk": {
+            "direction": "O"
+          },
+          "btn_trigger": {
+            "direction": "O"
+          },
+          "led_r": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "led_g": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          },
+          "led_b": {
+            "direction": "I",
+            "left": "7",
+            "right": "0"
+          }
+        }
       }
     },
     "interface_nets": {
@@ -1836,6 +1783,24 @@
           "LFO_0/s_axis"
         ]
       },
+      "axis_broadcaster_0_M00_AXIS": {
+        "interface_ports": [
+          "axis_broadcaster_0/M00_AXIS",
+          "axis_dual_i2s_0/s_axis"
+        ]
+      },
+      "axi4stream_spi_master_0_M_AXIS": {
+        "interface_ports": [
+          "axi4stream_spi_master_0/M_AXIS",
+          "digilent_jstk2_0/s_axis"
+        ]
+      },
+      "balance_controller_0_m_axis": {
+        "interface_ports": [
+          "balance_controller_0/m_axis",
+          "volume_controller_0/s_axis"
+        ]
+      },
       "mute_controller_0_m_axis": {
         "interface_ports": [
           "mute_controller_0/m_axis",
@@ -1848,29 +1813,11 @@
           "led_level_controller_0/s_axis"
         ]
       },
-      "axis_broadcaster_0_M00_AXIS": {
-        "interface_ports": [
-          "axis_broadcaster_0/M00_AXIS",
-          "axis_dual_i2s_0/s_axis"
-        ]
-      },
-      "balance_controller_0_m_axis": {
-        "interface_ports": [
-          "balance_controller_0/m_axis",
-          "volume_controller_0/s_axis"
-        ]
-      },
       "moving_average_filte_0_m_axis": {
         "interface_ports": [
           "balance_controller_0/s_axis",
           "moving_average_filte_0/m_axis"
         ]
-      },
-      "axi4stream_spi_master_0_M_AXIS": {
-        "interface_ports": [
-          "axi4stream_spi_master_0/M_AXIS",
-          "digilent_jstk2_0/s_axis"
-        ]
       }
     },
     "nets": {
@@ -1884,7 +1831,6 @@
         "ports": [
           "clk_wiz_0/clk_out1",
           "proc_sys_reset_0/slowest_sync_clk",
-          "digilent_jstk2_0/aclk",
           "edge_detector_toggle_0/clk",
           "edge_detector_toggle_1/clk",
           "debouncer_0/clk",
@@ -1897,7 +1843,8 @@
           "led_level_controller_0/aclk",
           "mute_controller_0/aclk",
           "axi4stream_spi_master_0/aclk",
-          "axis_dual_i2s_0/aclk"
+          "axis_dual_i2s_0/aclk",
+          "digilent_jstk2_0/aclk"
         ]
       },
       "reset_1": {
@@ -1925,7 +1872,6 @@
       "proc_sys_reset_0_peripheral_aresetn": {
         "ports": [
           "proc_sys_reset_0/peripheral_aresetn",
-          "digilent_jstk2_0/aresetn",
           "debouncer_0/reset",
           "axis_broadcaster_0/aresetn",
           "moving_average_filte_0/aresetn",
@@ -1936,7 +1882,8 @@
           "led_level_controller_0/aresetn",
           "mute_controller_0/aresetn",
           "axi4stream_spi_master_0/aresetn",
-          "axis_dual_i2s_0/aresetn"
+          "axis_dual_i2s_0/aresetn",
+          "digilent_jstk2_0/aresetn"
         ]
       },
       "proc_sys_reset_1_peripheral_aresetn": {

LAB3/design/lab_3/lab_3.bda

@@ -21,22 +21,22 @@
   <key attr.name="vert_type" attr.type="string" for="node" id="VT"/>
   <graph edgedefault="undirected" id="G" parse.edgeids="canonical" parse.nodeids="canonical" parse.order="nodesfirst">
     <node id="n0">
+      <data key="VM">lab_3</data>
+      <data key="VT">BC</data>
+    </node>
+    <node id="n1">
       <data key="VH">2</data>
       <data key="VM">lab_3</data>
       <data key="VT">VR</data>
     </node>
-    <node id="n1">
+    <node id="n2">
       <data key="TU">active</data>
       <data key="VH">2</data>
       <data key="VT">PM</data>
     </node>
-    <node id="n2">
+    <edge id="e0" source="n0" target="n1">
-      <data key="VM">lab_3</data>
-      <data key="VT">BC</data>
-    </node>
-    <edge id="e0" source="n2" target="n0">
     </edge>
-    <edge id="e1" source="n0" target="n1">
+    <edge id="e1" source="n1" target="n2">
     </edge>
   </graph>
 </graphml>

LAB3/src/digilent_jstk2.vhd

@@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY digilent_jstk2 IS
     GENERIC (
-        DELAY_US : INTEGER := 25; -- Delay (in us) between two packets
+        DELAY_US : INTEGER := 100; -- Delay (in us) between two packets
         CLKFREQ : INTEGER := 100_000_000; -- Frequency of the aclk signal (in Hz)
         SPI_SCLKFREQ : INTEGER := 5_000 -- Frequency of the SPI SCLK clock signal (in Hz)
     );
@@ -42,11 +42,11 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
     -- Do not forget that you MUST wait a bit between two packets. See the JSTK2 datasheet (and the SPI IP-Core README).
     ------------------------------------------------------------
 
-    CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000) - 1;
+    CONSTANT DELAY_CLK_CYCLES : INTEGER := DELAY_US * (CLKFREQ / 1_000_000);
 
     -- State machine states
-    TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY);
+    TYPE tx_state_type IS (DELAY, SEND_CMD, SEND_RED, SEND_GREEN, SEND_BLUE, SEND_DUMMY, WAIT_READY);
-    TYPE rx_state_type IS (IDLE, JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS);
+    TYPE rx_state_type IS (JSTK_X_LOW, JSTK_X_HIGH, JSTK_Y_LOW, JSTK_Y_HIGH, BUTTONS);
 
     SIGNAL tx_state : tx_state_type := DELAY;
     SIGNAL rx_state : rx_state_type := JSTK_X_LOW;
@@ -54,7 +54,6 @@ ARCHITECTURE Behavioral OF digilent_jstk2 IS
     SIGNAL tx_delay_counter : INTEGER := 0;
 
     SIGNAL rx_cache : STD_LOGIC_VECTOR(7 DOWNTO 0);
-    SIGNAL rx_done : STD_LOGIC := '1'; -- Pronto a trasmettere al primo ciclo
 
 BEGIN
     -- The SPI IP-Core is a slave, so we must set the m_axis_tvalid signal to '1' when we want to send data to it.
@@ -74,46 +73,49 @@ BEGIN
             ELSE
 
                 CASE tx_state IS
+
                     WHEN DELAY =>
-                        m_axis_tdata <= (OTHERS => '0');
                         IF tx_delay_counter >= DELAY_CLK_CYCLES THEN
-                            IF rx_done = '1' THEN
+                            tx_delay_counter <= 0;
-                                tx_delay_counter <= 0;
+                            tx_state <= SEND_CMD;
-                                tx_state <= SEND_CMD;
-                            END IF;
                         ELSE
                             tx_delay_counter <= tx_delay_counter + 1;
                         END IF;
 
                     WHEN SEND_CMD =>
+                        tx_state <= SEND_RED;
                         m_axis_tdata <= CMDSETLEDRGB;
-                        IF m_axis_tready = '1' THEN
-                            tx_state <= SEND_RED;
-                        END IF;
 
                     WHEN SEND_RED =>
-                        m_axis_tdata <= led_r;
                         IF m_axis_tready = '1' THEN
+                            m_axis_tdata <= led_r;
                             tx_state <= SEND_GREEN;
                         END IF;
 
                     WHEN SEND_GREEN =>
-                        m_axis_tdata <= led_g;
                         IF m_axis_tready = '1' THEN
+                            m_axis_tdata <= led_g;
                             tx_state <= SEND_BLUE;
                         END IF;
 
                     WHEN SEND_BLUE =>
-                        m_axis_tdata <= led_b;
                         IF m_axis_tready = '1' THEN
+                            m_axis_tdata <= led_b;
                             tx_state <= SEND_DUMMY;
                         END IF;
 
                     WHEN SEND_DUMMY =>
-                        m_axis_tdata <= (OTHERS => '0');
                         IF m_axis_tready = '1' THEN
+                            m_axis_tdata <= "01101000"; -- Dummy byte
+                            tx_state <= WAIT_READY;
+                        END IF;
+
+                    WHEN WAIT_READY =>
+                        IF m_axis_tready = '1' THEN
+                            m_axis_tdata <= "01000101"; -- Dummy byte not readed
                             tx_state <= DELAY;
                         END IF;
+
                 END CASE;
             END IF;
         END IF;
@@ -126,18 +128,12 @@ BEGIN
 
             IF aresetn = '0' THEN
 
-                rx_state <= IDLE;
+                rx_state <= JSTK_X_LOW;
                 rx_cache <= (OTHERS => '0');
-                rx_done <= '1';
 
             ELSE
-                
+
                 CASE rx_state IS
-                    WHEN IDLE =>
-                        IF tx_state = SEND_CMD THEN
-                            rx_state <= JSTK_X_LOW;
-                            rx_done <= '0'; -- In attesa di ricevere la risposta
-                        END IF;
 
                     WHEN JSTK_X_LOW =>
                         IF s_axis_tvalid = '1' THEN
@@ -167,9 +163,9 @@ BEGIN
                         IF s_axis_tvalid = '1' THEN
                             btn_jstk <= s_axis_tdata(0);
                             btn_trigger <= s_axis_tdata(1);
-                            rx_state <= IDLE;
+                            rx_state <= JSTK_X_LOW;
-                            rx_done <= '1'; -- Risposta completa ricevuta
                         END IF;
+
                 END CASE;
             END IF;
         END IF;

LAB3/test/uart_viewer.py

@@ -1,6 +1,10 @@
 import serial
 import serial.tools.list_ports
 import time
+import matplotlib.pyplot as plt
+import matplotlib.animation as animation
+import threading
+import queue
 
 # CONFIGURAZIONE
 BASYS3_PID = 0x6010
@@ -20,12 +24,43 @@ if not dev:
 PORT = dev
 
 def receive_mode(ser):
-    print("Modalità ricezione. Premi Ctrl+C per uscire.\n")
+    print("Modalità ricezione e visualizzazione coordinate in tempo reale. Premi Ctrl+C per uscire.\n")
-    while True:
+    q = queue.Queue()
-        if ser.in_waiting >= CHUNK_SIZE:
+
-            data = ser.read(CHUNK_SIZE)
+    def serial_reader():
-            hex_bytes = ' '.join(f"{b:02X}" for b in data)
+        while True:
-            print(f"HH | {hex_bytes}")
+            if ser.in_waiting >= CHUNK_SIZE:
+                data = ser.read(CHUNK_SIZE)
+                if len(data) >= 2:
+                    x = data[0]
+                    y = data[1]
+                    q.put((x, y))
+
+    reader_thread = threading.Thread(target=serial_reader, daemon=True)
+    reader_thread.start()
+
+    # Start with a single point at (0,0)
+    latest_point = [0, 0]
+
+    fig, ax = plt.subplots()
+    sc = ax.scatter([latest_point[0]], [latest_point[1]])
+    ax.set_xlim(0, 255)
+    ax.set_ylim(0, 255)
+    ax.set_xlabel("X")
+    ax.set_ylabel("Y")
+    ax.set_title("Coordinate in tempo reale")
+
+    def update(frame):
+        # Update only if new data is available
+        while not q.empty():
+            x, y = q.get()
+            latest_point[0] = x
+            latest_point[1] = y
+        sc.set_offsets([latest_point])  # Note the extra brackets!
+        return sc,
+
+    ani = animation.FuncAnimation(fig, update, interval=30, blit=True)
+    plt.show()
 
 def send_mode(ser):
     print("Modalità invio. Inserisci 3 byte in esadecimale (il primo sarà sempre 'C0').")

LAB3/vivado/diligent_jstk/diligent_jstk.xpr

@@ -55,13 +55,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="8"/>
+    <Option Name="WTXSimExportSim" Val="12"/>
-    <Option Name="WTModelSimExportSim" Val="8"/>
+    <Option Name="WTModelSimExportSim" Val="12"/>
-    <Option Name="WTQuestaExportSim" Val="8"/>
+    <Option Name="WTQuestaExportSim" Val="12"/>
-    <Option Name="WTIesExportSim" Val="8"/>
+    <Option Name="WTIesExportSim" Val="12"/>
-    <Option Name="WTVcsExportSim" Val="8"/>
+    <Option Name="WTVcsExportSim" Val="12"/>
-    <Option Name="WTRivieraExportSim" Val="8"/>
+    <Option Name="WTRivieraExportSim" Val="12"/>
-    <Option Name="WTActivehdlExportSim" Val="8"/>
+    <Option Name="WTActivehdlExportSim" Val="12"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -95,27 +95,6 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_clk_wiz_0_1/diligent_jstk_clk_wiz_0_1.xci">
-          <Proxy FileSetName="diligent_jstk_clk_wiz_0_1"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_proc_sys_reset_0_0/diligent_jstk_proc_sys_reset_0_0.xci">
-          <Proxy FileSetName="diligent_jstk_proc_sys_reset_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_AXI4Stream_UART_0_0/diligent_jstk_AXI4Stream_UART_0_0.xci">
-          <Proxy FileSetName="diligent_jstk_AXI4Stream_UART_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_jstk_uart_bridge_0_0/diligent_jstk_jstk_uart_bridge_0_0.xci">
-          <Proxy FileSetName="diligent_jstk_jstk_uart_bridge_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_axi4stream_spi_master_0_0/diligent_jstk_axi4stream_spi_master_0_0.xci">
-          <Proxy FileSetName="diligent_jstk_axi4stream_spi_master_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_digilent_jstk2_0_0/diligent_jstk_digilent_jstk2_0_0.xci">
-          <Proxy FileSetName="diligent_jstk_digilent_jstk2_0_0"/>
-        </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="diligent_jstk.bd" FileRelPathName="ip/diligent_jstk_system_ila_0_0/diligent_jstk_system_ila_0_0.xci">
-          <Proxy FileSetName="diligent_jstk_system_ila_0_0"/>
-        </CompFileExtendedInfo>
       </File>
       <File Path="$PPRDIR/../../design/diligent_jstk/hdl/diligent_jstk_wrapper.vhd">
         <FileInfo>
@@ -164,48 +143,6 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
-    <FileSet Name="diligent_jstk_proc_sys_reset_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_proc_sys_reset_0_0" RelGenDir="$PGENDIR/diligent_jstk_proc_sys_reset_0_0">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_proc_sys_reset_0_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="diligent_jstk_clk_wiz_0_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_clk_wiz_0_1" RelGenDir="$PGENDIR/diligent_jstk_clk_wiz_0_1">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_clk_wiz_0_1"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="diligent_jstk_AXI4Stream_UART_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_AXI4Stream_UART_0_0" RelGenDir="$PGENDIR/diligent_jstk_AXI4Stream_UART_0_0">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_AXI4Stream_UART_0_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="diligent_jstk_jstk_uart_bridge_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_jstk_uart_bridge_0_0" RelGenDir="$PGENDIR/diligent_jstk_jstk_uart_bridge_0_0">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_jstk_uart_bridge_0_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="diligent_jstk_axi4stream_spi_master_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_axi4stream_spi_master_0_0" RelGenDir="$PGENDIR/diligent_jstk_axi4stream_spi_master_0_0">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_axi4stream_spi_master_0_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="diligent_jstk_digilent_jstk2_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_digilent_jstk2_0_0" RelGenDir="$PGENDIR/diligent_jstk_digilent_jstk2_0_0">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_digilent_jstk2_0_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
-    <FileSet Name="diligent_jstk_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/diligent_jstk_system_ila_0_0" RelGenDir="$PGENDIR/diligent_jstk_system_ila_0_0">
-      <Config>
-        <Option Name="TopModule" Val="diligent_jstk_system_ila_0_0"/>
-        <Option Name="UseBlackboxStub" Val="1"/>
-      </Config>
-    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -227,78 +164,6 @@
   </Simulators>
   <Runs Version="1" Minor="15">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="diligent_jstk_proc_sys_reset_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_proc_sys_reset_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_proc_sys_reset_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_proc_sys_reset_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_proc_sys_reset_0_0_synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="diligent_jstk_clk_wiz_0_1_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_clk_wiz_0_1" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_clk_wiz_0_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_clk_wiz_0_1_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_clk_wiz_0_1_synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="diligent_jstk_AXI4Stream_UART_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_AXI4Stream_UART_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_AXI4Stream_UART_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_AXI4Stream_UART_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_AXI4Stream_UART_0_0_synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
-    <Run Id="diligent_jstk_jstk_uart_bridge_0_0_synth_1" Type="Ft3:Synth" SrcSet="diligent_jstk_jstk_uart_bridge_0_0" Part="xc7a35tcpg236-1" ConstrsSet="diligent_jstk_jstk_uart_bridge_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/diligent_jstk_jstk_uart_bridge_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/diligent_jstk_jstk_uart_bridge_0_0_synth_1">
-      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
-        <Step Id="synth_design"/>
-      </Strategy>
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
-      <RQSFiles/>
-    </Run>
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@@ -312,7 +177,9 @@
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       <Strategy Version="1" Minor="2">
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2020">
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+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
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@@ -328,129 +195,6 @@
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