240 lines
7.0 KiB
VHDL
240 lines
7.0 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 04/21/2025
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-- Design Name:
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-- Module Name: tb_depacketizer - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description: Testbench for depacketizer
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY tb_depacketizer IS
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END tb_depacketizer;
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ARCHITECTURE Behavioral OF tb_depacketizer IS
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COMPONENT depacketizer IS
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GENERIC (
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HEADER : INTEGER := 16#FF#;
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FOOTER : INTEGER := 16#F1#
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);
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PORT (
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clk : IN STD_LOGIC;
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aresetn : IN STD_LOGIC;
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s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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s_axis_tvalid : IN STD_LOGIC;
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s_axis_tready : OUT STD_LOGIC;
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m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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m_axis_tvalid : OUT STD_LOGIC;
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m_axis_tready : IN STD_LOGIC;
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m_axis_tlast : OUT STD_LOGIC
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);
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END COMPONENT;
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-- Constants
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CONSTANT HEADER : INTEGER := 16#FF#;
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CONSTANT FOOTER : INTEGER := 16#F1#;
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-- Signals
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL aresetn : STD_LOGIC := '0';
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SIGNAL s_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
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SIGNAL s_axis_tvalid : STD_LOGIC := '0';
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SIGNAL s_axis_tready : STD_LOGIC;
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SIGNAL m_axis_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL m_axis_tvalid : STD_LOGIC;
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SIGNAL m_axis_tready : STD_LOGIC := '1';
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SIGNAL m_axis_tlast : STD_LOGIC;
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-- Stimulus memory
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TYPE mem_type IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL mem : mem_type := (
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0 => x"10",
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1 => x"20",
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2 => x"30",
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3 => x"04",
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4 => x"54",
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5 => x"65",
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6 => x"73",
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7 => x"50"
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);
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SIGNAL tready_block_req : STD_LOGIC := '0';
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BEGIN
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-- Clock generation
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clk <= NOT clk AFTER 5 ns;
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-- Asynchronous tready block process
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PROCESS (clk)
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VARIABLE block_counter : INTEGER := 0;
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VARIABLE tready_blocked : BOOLEAN := FALSE;
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BEGIN
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IF rising_edge(clk) THEN
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IF tready_block_req = '1' AND NOT tready_blocked THEN
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tready_blocked := TRUE;
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block_counter := 0;
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END IF;
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IF tready_blocked THEN
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IF block_counter < 9 THEN
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m_axis_tready <= '0';
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block_counter := block_counter + 1;
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ELSE
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m_axis_tready <= '1';
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tready_blocked := FALSE;
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block_counter := 0;
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END IF;
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ELSE
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m_axis_tready <= '1';
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END IF;
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END IF;
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END PROCESS;
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-- DUT instantiation
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uut: depacketizer
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PORT MAP (
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clk => clk,
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aresetn => aresetn,
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s_axis_tdata => s_axis_tdata,
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s_axis_tvalid => s_axis_tvalid,
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s_axis_tready => s_axis_tready,
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m_axis_tdata => m_axis_tdata,
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m_axis_tvalid => m_axis_tvalid,
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m_axis_tready => m_axis_tready,
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m_axis_tlast => m_axis_tlast
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);
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-- Stimulus process
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PROCESS
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BEGIN
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-- Reset
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aresetn <= '0';
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WAIT FOR 20 ns;
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aresetn <= '1';
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WAIT UNTIL rising_edge(clk);
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-- Start tready block asynchronously after 60 ns
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WAIT FOR 60 ns;
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tready_block_req <= '1';
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WAIT UNTIL rising_edge(clk);
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tready_block_req <= '0';
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-- Send 4 data words as a packet with Header and Footer
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-- Header
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Data
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FOR i IN 0 TO 3 LOOP
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s_axis_tdata <= mem(i);
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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END LOOP;
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-- Footer
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Wait a bit, then send another packet of 2 words with Header and Footer
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WAIT FOR 50 ns;
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-- Header
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Data
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FOR i IN 4 TO 5 LOOP
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s_axis_tdata <= mem(i);
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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END LOOP;
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-- Footer
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Start another tready block asynchronously
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WAIT FOR 40 ns;
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tready_block_req <= '1';
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WAIT UNTIL rising_edge(clk);
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tready_block_req <= '0';
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-- Send packet of 3 words with Header and Footer
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WAIT FOR 30 ns;
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-- Header
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Data
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FOR i IN 5 TO 7 LOOP
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s_axis_tdata <= mem(i);
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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END LOOP;
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-- Footer
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Send packet of 4 words without initial waiting, with Header and Footer
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-- Header
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(HEADER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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-- Data
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FOR i IN 2 TO 6 LOOP
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s_axis_tdata <= mem(i);
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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END LOOP;
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-- Footer
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s_axis_tdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(FOOTER, 8));
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s_axis_tvalid <= '1';
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WAIT UNTIL s_axis_tvalid = '1' AND s_axis_tready = '1' AND rising_edge(clk);
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s_axis_tvalid <= '0';
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WAIT;
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END PROCESS;
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END Behavioral; |